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| author | M R Swami Reddy <MR.Swami.Reddy@nsc.com> | 2008-05-05 09:52:46 +0000 |
|---|---|---|
| committer | M R Swami Reddy <MR.Swami.Reddy@nsc.com> | 2008-05-05 09:52:46 +0000 |
| commit | fae9ec8dca2e5d4da931451946f220271b5c5003 (patch) | |
| tree | 0e0e2407ebca338d7f49022432af2c951040a40f /sim/testsuite | |
| parent | e2b7ddeae30ddeb4056206b07d075e65bdf286ba (diff) | |
| download | fsf-binutils-gdb-fae9ec8dca2e5d4da931451946f220271b5c5003.zip fsf-binutils-gdb-fae9ec8dca2e5d4da931451946f220271b5c5003.tar.gz fsf-binutils-gdb-fae9ec8dca2e5d4da931451946f220271b5c5003.tar.bz2 | |
Update testcase comment.
addb.cgs addd.cgs addi.cgs andb.cgs andd.cgs andw.cgs
ashub.cgs ashub_i.cgs ashud.cgs ashud_i.cgs ashuw.cgs
ashuw_i.cgs cmpi.cgs cmpw.cgs jlt.cgs jump.cgs loadd.cgs
loadw.cgs lshb.cgs lshb_i.cgs lshd.cgs lshd_i.cgs lshw.cgs
lshw_i.cgs movb.cgs movd.cgs movw.cgs movxb.cgs movxw.cgs
movzb.cgs movzw.cgs mulb.cgs muluw.cgs mulw.cgs orb.cgs
ord.cgs orw.cgs pop1.cgs pop2.cgs pop3.cgs popret1.cgs
popret2.cgs popret3.cgs push1.cgs push2.cgs push3.cgs
Added BIT operation testcases:
cbitb.cgs cbitw.cgs sbitb.cgs sbitw.cgs tbitb.cgs tbit.cgs and tbitw.cgs
Diffstat (limited to 'sim/testsuite')
53 files changed, 315 insertions, 60 deletions
diff --git a/sim/testsuite/sim/cr16/addb.cgs b/sim/testsuite/sim/cr16/addb.cgs index 020f0fc..272804a 100644 --- a/sim/testsuite/sim/cr16/addb.cgs +++ b/sim/testsuite/sim/cr16/addb.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for addb $dr,$sr +# cr16 testcase for addb $sr, reg # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/addd.cgs b/sim/testsuite/sim/cr16/addd.cgs index cf9a975..c13164d 100644 --- a/sim/testsuite/sim/cr16/addd.cgs +++ b/sim/testsuite/sim/cr16/addd.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for addd $sr,$dr +# cr16 testcase for addd $sr, regp # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/addi.cgs b/sim/testsuite/sim/cr16/addi.cgs index 5d0fa1a..dae8941 100644 --- a/sim/testsuite/sim/cr16/addi.cgs +++ b/sim/testsuite/sim/cr16/addi.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for addi #$simm8, $dr +# cr16 testcase for addi $imm8, $dr # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/andb.cgs b/sim/testsuite/sim/cr16/andb.cgs index 56d1083..bc201ad 100644 --- a/sim/testsuite/sim/cr16/andb.cgs +++ b/sim/testsuite/sim/cr16/andb.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for and $dr,$sr +# cr16 testcase for and $sr,$dr # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/andd.cgs b/sim/testsuite/sim/cr16/andd.cgs index 3951bf7..8e72bae 100644 --- a/sim/testsuite/sim/cr16/andd.cgs +++ b/sim/testsuite/sim/cr16/andd.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for and $dr,$sr +# cr16 testcase for and $sr,$dr # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/andw.cgs b/sim/testsuite/sim/cr16/andw.cgs index 20bb370..d2d634a 100644 --- a/sim/testsuite/sim/cr16/andw.cgs +++ b/sim/testsuite/sim/cr16/andw.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for and $dr,$sr +# cr16 testcase for and $sr,$dr # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/ashub.cgs b/sim/testsuite/sim/cr16/ashub.cgs index b3113e1..ef3e94e 100644 --- a/sim/testsuite/sim/cr16/ashub.cgs +++ b/sim/testsuite/sim/cr16/ashub.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for ashub $dr,$sr +# cr16 testcase for ashub $sr,$dr # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/ashub_i.cgs b/sim/testsuite/sim/cr16/ashub_i.cgs index ce0af1d..b4765a4 100644 --- a/sim/testsuite/sim/cr16/ashub_i.cgs +++ b/sim/testsuite/sim/cr16/ashub_i.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for ashub $dr,$sr +# cr16 testcase for ashub $sr,$dr # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/ashud.cgs b/sim/testsuite/sim/cr16/ashud.cgs index 91b6e75..c9511da 100644 --- a/sim/testsuite/sim/cr16/ashud.cgs +++ b/sim/testsuite/sim/cr16/ashud.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for ashud $dr,$sr +# cr16 testcase for ashud $sr,$dr # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/ashud_i.cgs b/sim/testsuite/sim/cr16/ashud_i.cgs index 3b45797..3beb4e3 100644 --- a/sim/testsuite/sim/cr16/ashud_i.cgs +++ b/sim/testsuite/sim/cr16/ashud_i.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for ashud $dr,$sr +# cr16 testcase for ashud $sr,$dr # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/ashuw.cgs b/sim/testsuite/sim/cr16/ashuw.cgs index 8ef3cf7..8f52e35 100644 --- a/sim/testsuite/sim/cr16/ashuw.cgs +++ b/sim/testsuite/sim/cr16/ashuw.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for ashuw $dr,$sr +# cr16 testcase for ashuw $sr,$dr # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/ashuw_i.cgs b/sim/testsuite/sim/cr16/ashuw_i.cgs index 0a8322a..9925914 100644 --- a/sim/testsuite/sim/cr16/ashuw_i.cgs +++ b/sim/testsuite/sim/cr16/ashuw_i.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for ashuw $dr,$sr +# cr16 testcase for ashuw $sr,$dr # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/cbitb.cgs b/sim/testsuite/sim/cr16/cbitb.cgs new file mode 100644 index 0000000..473fd71 --- /dev/null +++ b/sim/testsuite/sim/cr16/cbitb.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for cbitb $bit_pos, ABS/REGP/REG +# mach: cr16 + + .include "testutils.inc" + + start + + .global cbitb +cbitb: + cbitb $0,_y + loadw _y, r1 + cmpb $0xfe, r1 + beq ok1 +not_ok: + fail + +ok1: + movd $_y, (r1,r0) + cbitb $1,0(r1,r0) + loadw _y, r1 + cmpb $0xfc, r1 + beq ok2 + br not_ok +ok2: + + movw $_y, r1 + cbitb $2,0(r1) + loadw _y, r1 + cmpb $0xf8, r1 + beq ok3 + br not_ok +ok3: + pass + +_y: .word 0xff diff --git a/sim/testsuite/sim/cr16/cbitw.cgs b/sim/testsuite/sim/cr16/cbitw.cgs new file mode 100644 index 0000000..a97698c --- /dev/null +++ b/sim/testsuite/sim/cr16/cbitw.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for cbitw +# mach: cr16 + + .include "testutils.inc" + + start + + .global cbitw +cbitw: + cbitw $4,_y + loadw _y, r1 + cmpb $0xef, r1 + beq ok1 +not_ok: + fail + +ok1: + movd $_y, (r1,r0) + cbitw $5,0(r1,r0) + loadw _y, r1 + cmpb $0xcf, r1 + beq ok2 + br not_ok +ok2: + + movw $_y, r1 + cbitw $6,0(r1) + loadw _y, r1 + cmpb $0x8f, r1 + beq ok3 + br not_ok +ok3: + pass + +_y: .word 0xff diff --git a/sim/testsuite/sim/cr16/cmpi.cgs b/sim/testsuite/sim/cr16/cmpi.cgs index e7302b8..cff17e8 100644 --- a/sim/testsuite/sim/cr16/cmpi.cgs +++ b/sim/testsuite/sim/cr16/cmpi.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for cmpi $src2,#$simm16 +# cr16 testcase for cmpi $imm16, reg # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/cmpw.cgs b/sim/testsuite/sim/cr16/cmpw.cgs index 5570a10..9d333fb 100644 --- a/sim/testsuite/sim/cr16/cmpw.cgs +++ b/sim/testsuite/sim/cr16/cmpw.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for cmp $src1,$src2 +# cr16 testcase for cmp $imm, reg # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/jlt.cgs b/sim/testsuite/sim/cr16/jlt.cgs index 99c1862..ca93cf1 100644 --- a/sim/testsuite/sim/cr16/jlt.cgs +++ b/sim/testsuite/sim/cr16/jlt.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for jlt (repl) +# cr16 testcase for jlt (regp) # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/jump.cgs b/sim/testsuite/sim/cr16/jump.cgs index b2b4774..df20c15 100644 --- a/sim/testsuite/sim/cr16/jump.cgs +++ b/sim/testsuite/sim/cr16/jump.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for jmp $sr +# cr16 testcase for jmp (regp) # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/loadd.cgs b/sim/testsuite/sim/cr16/loadd.cgs index 0330687..b6a851d 100644 --- a/sim/testsuite/sim/cr16/loadd.cgs +++ b/sim/testsuite/sim/cr16/loadd.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for ldb $dr,@$sr +# cr16 testcase for loadd 0(regp),regp # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/loadw.cgs b/sim/testsuite/sim/cr16/loadw.cgs index 47d92ad..8faf616 100644 --- a/sim/testsuite/sim/cr16/loadw.cgs +++ b/sim/testsuite/sim/cr16/loadw.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for ldb $dr,@$sr +# cr16 testcase for loadw 0(regp), (regp) # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/lshb.cgs b/sim/testsuite/sim/cr16/lshb.cgs index 877f33f..59ddbba 100644 --- a/sim/testsuite/sim/cr16/lshb.cgs +++ b/sim/testsuite/sim/cr16/lshb.cgs @@ -1,12 +1,12 @@ -# cr16 testcase for sll $dr,$sr +# cr16 testcase for lshb count, reg # mach(): cr16 .include "testutils.inc" start - .global sll -sll: + .global lshb +lshb: movb $6, r4 movb $1, r5 lshb r5, r4 diff --git a/sim/testsuite/sim/cr16/lshb_i.cgs b/sim/testsuite/sim/cr16/lshb_i.cgs index 5302183..10d3085 100644 --- a/sim/testsuite/sim/cr16/lshb_i.cgs +++ b/sim/testsuite/sim/cr16/lshb_i.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for lshb_i $dr,#$uimm5 +# cr16 testcase for lshb_i $uimm5, reg # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/lshd.cgs b/sim/testsuite/sim/cr16/lshd.cgs index d455407..e146ca1 100644 --- a/sim/testsuite/sim/cr16/lshd.cgs +++ b/sim/testsuite/sim/cr16/lshd.cgs @@ -1,12 +1,12 @@ -# cr16 testcase for sll $dr,$sr +# cr16 testcase for lshd reg, regp # mach(): cr16 .include "testutils.inc" start - .global sll -sll: + .global lshd +lshd: movd $0x12345678, (r4,r3) movw $0x10, r5 lshd r5, (r4,r3) diff --git a/sim/testsuite/sim/cr16/lshd_i.cgs b/sim/testsuite/sim/cr16/lshd_i.cgs index b517f38..aa65933 100644 --- a/sim/testsuite/sim/cr16/lshd_i.cgs +++ b/sim/testsuite/sim/cr16/lshd_i.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for lshb_i $dr,#$uimm5 +# cr16 testcase for lshb_i $uimm5, regp # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/lshw.cgs b/sim/testsuite/sim/cr16/lshw.cgs index 536fe2f..a10edff 100644 --- a/sim/testsuite/sim/cr16/lshw.cgs +++ b/sim/testsuite/sim/cr16/lshw.cgs @@ -1,12 +1,12 @@ -# cr16 testcase for sll $dr,$sr +# cr16 testcase for lshw reg, reg # mach(): cr16 .include "testutils.inc" start - .global sll -sll: + .global lshw +lshw: movw $0x1234, r4 movw $8, r5 lshw r5, r4 diff --git a/sim/testsuite/sim/cr16/lshw_i.cgs b/sim/testsuite/sim/cr16/lshw_i.cgs index c559f49..9e94a5e 100644 --- a/sim/testsuite/sim/cr16/lshw_i.cgs +++ b/sim/testsuite/sim/cr16/lshw_i.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for lshb_i $dr,#$uimm5 +# cr16 testcase for lshb_i $uimm4, reg # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/movb.cgs b/sim/testsuite/sim/cr16/movb.cgs index e235670..fc8fcba 100644 --- a/sim/testsuite/sim/cr16/movb.cgs +++ b/sim/testsuite/sim/cr16/movb.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for movb $sr,$dr +# cr16 testcase for movb $imm, reg # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/movd.cgs b/sim/testsuite/sim/cr16/movd.cgs index 8e77b5a..8b1b638 100644 --- a/sim/testsuite/sim/cr16/movd.cgs +++ b/sim/testsuite/sim/cr16/movd.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for movd $sr,$dr +# cr16 testcase for movd $imm32, regp # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/movw.cgs b/sim/testsuite/sim/cr16/movw.cgs index cd92cba..e14afb0 100644 --- a/sim/testsuite/sim/cr16/movw.cgs +++ b/sim/testsuite/sim/cr16/movw.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for movw $sr,$dr +# cr16 testcase for movw $imm16, reg # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/movxb.cgs b/sim/testsuite/sim/cr16/movxb.cgs index 301e9af..3c356c9 100644 --- a/sim/testsuite/sim/cr16/movxb.cgs +++ b/sim/testsuite/sim/cr16/movxb.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for movb $sr,$dr +# cr16 testcase for movb $imm4, reg # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/movxw.cgs b/sim/testsuite/sim/cr16/movxw.cgs index 44d9549..77dea80 100644 --- a/sim/testsuite/sim/cr16/movxw.cgs +++ b/sim/testsuite/sim/cr16/movxw.cgs @@ -1,4 +1,4 @@ -# cr16 testcase for movw $sr,$dr +# cr16 testcase for movw reg, regp # mach(): cr16 .include "testutils.inc" diff --git a/sim/testsuite/sim/cr16/movzb.cgs b/sim/testsuite/sim/cr16/movzb.cgs index e4de4b0..acbe2b6 100644 --- a/sim/testsuite/sim/cr16/movzb.cgs +++ b/sim/testsuite/sim/cr16/movzb.cgs @@ -1,12 +1,12 @@ -# cr16 testcase for movb $sr,$dr +# cr16 testcase for movzb reg, reg # mach(): cr16 .include "testutils.inc" start - .global movb -movb: + .global movzb +movzb: movw $0x120f, r4 movw $0x1200, r5 diff --git a/sim/testsuite/sim/cr16/movzw.cgs b/sim/testsuite/sim/cr16/movzw.cgs index f3f5835..93855e4 100644 --- a/sim/testsuite/sim/cr16/movzw.cgs +++ b/sim/testsuite/sim/cr16/movzw.cgs @@ -1,12 +1,12 @@ -# cr16 testcase for movw $sr,$dr +# cr16 testcase for movzw reg, regp # mach(): cr16 .include "testutils.inc" start - .global movw -movw: + .global movzw +movzw: movb $0xff, r4 movd $0x12345678,(r6, r5) diff --git a/sim/testsuite/sim/cr16/mulb.cgs b/sim/testsuite/sim/cr16/mulb.cgs index 6b77cb2..c4b859f 100644 --- a/sim/testsuite/sim/cr16/mulb.cgs +++ b/sim/testsuite/sim/cr16/mulb.cgs @@ -7,11 +7,11 @@ .global mulb mulb: - movw $0x2303,r4 - movw $0x1207,r5 + movw $0x1234,r4 + movw $0x4567,r5 mulb r4, r5 - cmpb $21, r5 + cmpb $0xec, r5 beq ok1 not_ok: fail diff --git a/sim/testsuite/sim/cr16/muluw.cgs b/sim/testsuite/sim/cr16/muluw.cgs index 3005a98..71f7ee0 100644 --- a/sim/testsuite/sim/cr16/muluw.cgs +++ b/sim/testsuite/sim/cr16/muluw.cgs @@ -1,16 +1,16 @@ -# cr16 testcase for mul $dr,$sr +# cr16 testcase for muluw reg, regp # mach(): cr16 .include "testutils.inc" start - .global mul -mul: + .global muluw +muluw: movw $0xfff,r4 # fix for 0xffff movd $0xffffffff,(r6,r5) muluw r4, (r6,r5) - test_h_grp "(r6,r5)", 0xfffff001 + test_h_grp "(r6,r5)", 0xffef001 pass diff --git a/sim/testsuite/sim/cr16/mulw.cgs b/sim/testsuite/sim/cr16/mulw.cgs index bee87fa..cbd4552 100644 --- a/sim/testsuite/sim/cr16/mulw.cgs +++ b/sim/testsuite/sim/cr16/mulw.cgs @@ -1,12 +1,12 @@ -# cr16 testcase for mul $dr,$sr +# cr16 testcase for mulw reg reg # mach(): cr16 .include "testutils.inc" start - .global mul -mul: + .global mulw +mulw: movw $0x1234,r4 movw $0x1234,r5 diff --git a/sim/testsuite/sim/cr16/orb.cgs b/sim/testsuite/sim/cr16/orb.cgs index 61f7f6e..43ce26b 100644 --- a/sim/testsuite/sim/cr16/orb.cgs +++ b/sim/testsuite/sim/cr16/orb.cgs @@ -1,12 +1,12 @@ -# cr16 testcase for or $sr,$dr +# cr16 testcase for orb $imm, reg # mach(): cr16 .include "testutils.inc" start - .global or -or: + .global orb +orb: movb $3, r4 movb $6, r5 diff --git a/sim/testsuite/sim/cr16/ord.cgs b/sim/testsuite/sim/cr16/ord.cgs index b295f04..e682d3a 100644 --- a/sim/testsuite/sim/cr16/ord.cgs +++ b/sim/testsuite/sim/cr16/ord.cgs @@ -1,12 +1,12 @@ -# cr16 testcase for or $dr,$sr +# cr16 testcase for ord $imm32, regp # mach(): cr16 .include "testutils.inc" start - .global or -or: + .global ord +ord: movd $0x33333333, (r4,r3) movd $0x66666666, (r6,r5) diff --git a/sim/testsuite/sim/cr16/orw.cgs b/sim/testsuite/sim/cr16/orw.cgs index 138af88..4c1b529 100644 --- a/sim/testsuite/sim/cr16/orw.cgs +++ b/sim/testsuite/sim/cr16/orw.cgs @@ -1,12 +1,12 @@ -# cr16 testcase for or $dr,$sr +# cr16 testcase for orw reg, reg # mach(): cr16 .include "testutils.inc" start - .global or -or: + .global orw +orw: movw $3, r4 movw $6, r5 diff --git a/sim/testsuite/sim/cr16/pop1.cgs b/sim/testsuite/sim/cr16/pop1.cgs index 9ac4630..cf2a02d 100644 --- a/sim/testsuite/sim/cr16/pop1.cgs +++ b/sim/testsuite/sim/cr16/pop1.cgs @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global pop1 pop1: movd $0x1000, (sp) movw $0x2f50, r3 diff --git a/sim/testsuite/sim/cr16/pop2.cgs b/sim/testsuite/sim/cr16/pop2.cgs index 808f01e..aa3a9ec 100644 --- a/sim/testsuite/sim/cr16/pop2.cgs +++ b/sim/testsuite/sim/cr16/pop2.cgs @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global pop2 pop2: movd $0x1000, (sp) movw $0x2f50, r3 diff --git a/sim/testsuite/sim/cr16/pop3.cgs b/sim/testsuite/sim/cr16/pop3.cgs index 35d893d..13478f1 100644 --- a/sim/testsuite/sim/cr16/pop3.cgs +++ b/sim/testsuite/sim/cr16/pop3.cgs @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global pop3 pop3: movd $0x1006, (sp) movd $0xabcd, (r3,r2) diff --git a/sim/testsuite/sim/cr16/popret1.cgs b/sim/testsuite/sim/cr16/popret1.cgs index aab42b3..a34b0fb 100644 --- a/sim/testsuite/sim/cr16/popret1.cgs +++ b/sim/testsuite/sim/cr16/popret1.cgs @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global popret1 popret1: movd $0x1000, (sp) movw $0x2f50, r3 diff --git a/sim/testsuite/sim/cr16/popret2.cgs b/sim/testsuite/sim/cr16/popret2.cgs index 5ad65c5..5a7f905 100644 --- a/sim/testsuite/sim/cr16/popret2.cgs +++ b/sim/testsuite/sim/cr16/popret2.cgs @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global popret2 popret2: movd $0x1000, (sp) movw $0x2f50, r3 diff --git a/sim/testsuite/sim/cr16/popret3.cgs b/sim/testsuite/sim/cr16/popret3.cgs index c9c79df..31aaa9b 100644 --- a/sim/testsuite/sim/cr16/popret3.cgs +++ b/sim/testsuite/sim/cr16/popret3.cgs @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global popret3 popret3: movd $0x1006, (sp) movd $ok, (ra) diff --git a/sim/testsuite/sim/cr16/push1.cgs b/sim/testsuite/sim/cr16/push1.cgs index 025a69f..12d50a6 100644 --- a/sim/testsuite/sim/cr16/push1.cgs +++ b/sim/testsuite/sim/cr16/push1.cgs @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global push1 push1: movd $0x100a, (sp) movd $0xabcd, (ra) diff --git a/sim/testsuite/sim/cr16/push2.cgs b/sim/testsuite/sim/cr16/push2.cgs index d6bd1b6..76c1a37 100644 --- a/sim/testsuite/sim/cr16/push2.cgs +++ b/sim/testsuite/sim/cr16/push2.cgs @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global push2 push2: movd $0x1006, (sp) movw $0x2f50, r5 diff --git a/sim/testsuite/sim/cr16/push3.cgs b/sim/testsuite/sim/cr16/push3.cgs index 6dbf04d..f9f5c26 100644 --- a/sim/testsuite/sim/cr16/push3.cgs +++ b/sim/testsuite/sim/cr16/push3.cgs @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global push1 push1: movd $0x1006, (sp) movd $0xabcd, (ra) diff --git a/sim/testsuite/sim/cr16/sbitb.cgs b/sim/testsuite/sim/cr16/sbitb.cgs new file mode 100644 index 0000000..b98329c --- /dev/null +++ b/sim/testsuite/sim/cr16/sbitb.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for sbitb $count, reg/regp/mem +# mach: cr16 + + .include "testutils.inc" + + start + + .global sbitb +sbitb: + sbitb $0,_y + loadw _y, r1 + cmpb $0xf1, r1 + beq ok1 +not_ok: + fail + +ok1: + movd $_y, (r1,r0) + sbitb $1,0(r1,r0) + loadw _y, r1 + cmpb $0xf3, r1 + beq ok2 + br not_ok +ok2: + + movw $_y, r1 + sbitb $2,0(r1) + loadw _y, r1 + cmpb $0xf7, r1 + beq ok3 + br not_ok +ok3: + pass + +_y: .word 0xf0 diff --git a/sim/testsuite/sim/cr16/sbitw.cgs b/sim/testsuite/sim/cr16/sbitw.cgs new file mode 100644 index 0000000..2a9a828 --- /dev/null +++ b/sim/testsuite/sim/cr16/sbitw.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for sbitw +# mach: cr16 + + .include "testutils.inc" + + start + + .global sbitw +sbitw: + sbitw $4,_y + loadw _y, r1 + cmpb $0x1f, r1 + beq ok1 +not_ok: + fail + +ok1: + movd $_y, (r1,r0) + sbitw $5,0(r1,r0) + loadw _y, r1 + cmpb $0x3f, r1 + beq ok2 + br not_ok +ok2: + + movw $_y, r1 + sbitw $6,0(r1) + loadw _y, r1 + cmpb $0x7f, r1 + beq ok3 + br not_ok +ok3: + pass + +_y: .word 0x0f diff --git a/sim/testsuite/sim/cr16/tbit.cgs b/sim/testsuite/sim/cr16/tbit.cgs new file mode 100644 index 0000000..ac1b7e2 --- /dev/null +++ b/sim/testsuite/sim/cr16/tbit.cgs @@ -0,0 +1,31 @@ +# cr16 testcase for tbit +# mach: cr16 + + .include "testutils.inc" + + start + + .global tbit +tbit: + movw $0, r1 + lpr r1, psr + movw $0x7, r1 + tbit $0, r1 + spr psr, r1 + cmpb $0x20, r1 + beq ok1 +not_ok: + fail + +ok1: + movw $0, r1 + lpr r1, psr + movw $0xa, r1 + movw $0x1, r2 + tbit r2,r1 + spr psr, r1 + cmpb $0x20, r1 + beq ok2 + br not_ok +ok2: + pass diff --git a/sim/testsuite/sim/cr16/tbitb.cgs b/sim/testsuite/sim/cr16/tbitb.cgs new file mode 100644 index 0000000..57a8ab2 --- /dev/null +++ b/sim/testsuite/sim/cr16/tbitb.cgs @@ -0,0 +1,33 @@ +# cr16 testcase for tbitb +# mach: cr16 + + .include "testutils.inc" + + start + + .global tbitb +tbitb: + movw $0, r1 + lpr r1, psr + movw $_y, r1 + tbitb $0, 0(r1) + spr psr, r1 + cmpb $0x20, r1 + beq ok1 +not_ok: + fail + +ok1: + movw $0, r1 + lpr r1, psr + movd $_y, (r1,r0) + tbitb $1,0(r1,r0) + spr psr, r1 + cmpb $0x20, r1 + beq ok2 + br not_ok +ok2: + + pass + +_y: .word 0xf7 diff --git a/sim/testsuite/sim/cr16/tbitw.cgs b/sim/testsuite/sim/cr16/tbitw.cgs new file mode 100644 index 0000000..018c73e --- /dev/null +++ b/sim/testsuite/sim/cr16/tbitw.cgs @@ -0,0 +1,33 @@ +# cr16 testcase for tbitw +# mach: cr16 + + .include "testutils.inc" + + start + + .global tbitw +tbitw: + movw $0, r1 + lpr r1, psr + tbitw $0,_y + spr psr, r1 + cmpb $0x20, r1 + beq ok1 +not_ok: + fail + +ok1: + movw $0, r1 + lpr r1, psr + movd $_y, (r1,r0) + tbitw $1,0(r1,r0) + loadw _y, r1 + spr psr, r1 + cmpb $0x20, r1 + beq ok2 + br not_ok +ok2: + + pass + +_y: .word 0xf7 |