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author | Mike Frysinger <vapier@gentoo.org> | 2022-12-22 23:10:38 -0500 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2022-12-23 08:32:58 -0500 |
commit | f3e1a3e6fa80c20b7ab5e968330ae69fe0a3cd81 (patch) | |
tree | bbc68dacd2636833055dff2bb4057171c212fd02 /sim/riscv/sim-main.h | |
parent | f625c714c2c5a9b6fdc5f4424730e6140c8d0bb9 (diff) | |
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sim: riscv: move arch-specific settings to internal header
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
We can also move the machs.h include out since the model logic was all
generalized from compile-time to runtime last year.
Diffstat (limited to 'sim/riscv/sim-main.h')
-rw-r--r-- | sim/riscv/sim-main.h | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/sim/riscv/sim-main.h b/sim/riscv/sim-main.h index 48ea452..a6de53c 100644 --- a/sim/riscv/sim-main.h +++ b/sim/riscv/sim-main.h @@ -22,61 +22,6 @@ #define SIM_MAIN_H #include "sim-basics.h" -#include "machs.h" #include "sim-base.h" -struct riscv_sim_cpu { - union { - unsigned_word regs[32]; - struct { - /* These are the ABI names. */ - unsigned_word zero, ra, sp, gp, tp; - unsigned_word t0, t1, t2; - unsigned_word s0, s1; - unsigned_word a0, a1, a2, a3, a4, a5, a6, a7; - unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11; - unsigned_word t3, t4, t5, t6; - }; - }; - union { - unsigned_word fpregs[32]; - struct { - /* These are the ABI names. */ - unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7; - unsigned_word fs0, fs1; - unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7; - unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11; - unsigned_word ft8, ft9, ft10, ft11; - }; - }; - sim_cia pc; - - struct { -#define DECLARE_CSR(name, ...) unsigned_word name; -#include "opcode/riscv-opc.h" -#undef DECLARE_CSR - } csr; -}; -#define RISCV_SIM_CPU(cpu) ((struct riscv_sim_cpu *) CPU_ARCH_DATA (cpu)) - -struct atomic_mem_reserved_list; -struct atomic_mem_reserved_list { - struct atomic_mem_reserved_list *next; - address_word addr; -}; - -struct riscv_sim_state { - struct atomic_mem_reserved_list *amo_reserved_list; -}; -#define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd)) - -extern void step_once (SIM_CPU *); -extern void initialize_cpu (SIM_DESC, SIM_CPU *, int); -extern void initialize_env (SIM_DESC, const char * const *argv, - const char * const *env); - -#define DEFAULT_MEM_SIZE (64 * 1024 * 1024) - -#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu)) - #endif |