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authorMike Frysinger <vapier@gentoo.org>2021-06-28 22:07:44 -0400
committerMike Frysinger <vapier@gentoo.org>2021-06-30 02:57:45 -0400
commitd414eb3e7fc1e82d68e69ba6a9a867b9d9a9dba2 (patch)
treec82ef917cb7fabce6d96e5357474f398b7de73be /sim/riscv/interp.c
parent1c636da093f335cd57e7fca0fc25ae9f9e849264 (diff)
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sim: move default model to the runtime sim state
This kills off another compile-time option by moving the setting to the individual arch runtimes. This will allow dynamic selection by the arch when doing a single build with multiple arches. The sim_model_init rework is a little funky. In the past it was disabled entirely if no default model was set. We maintain the spirit of the logic by gating the fallback logic on whether the port has defined any models.
Diffstat (limited to 'sim/riscv/interp.c')
-rw-r--r--sim/riscv/interp.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index 8908ed1..202412a 100644
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -66,6 +66,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
/* Set default options before parsing user options. */
STATE_MACHS (sd) = riscv_sim_machs;
+ STATE_MODEL_NAME (sd) = WITH_TARGET_WORD_BITSIZE == 32 ? "RV32G" : "RV64G";
current_target_byte_order = BFD_ENDIAN_LITTLE;
/* The cpu data is kept in a separately allocated chunk of memory. */