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author | Stafford Horne <shorne@gmail.com> | 2019-06-13 21:27:09 +0900 |
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committer | Stafford Horne <shorne@gmail.com> | 2019-06-13 21:27:09 +0900 |
commit | 7ccbb4437a29896955a6ff3b0406b1cc2a7f6fe2 (patch) | |
tree | bd7c4ad6a0b33e2fc26cd2b817c41828c975fe0b /sim/or1k/model.c | |
parent | 66eb1ed3882aa3c54daa2fe24b7479b5ee0538f2 (diff) | |
download | fsf-binutils-gdb-7ccbb4437a29896955a6ff3b0406b1cc2a7f6fe2.zip fsf-binutils-gdb-7ccbb4437a29896955a6ff3b0406b1cc2a7f6fe2.tar.gz fsf-binutils-gdb-7ccbb4437a29896955a6ff3b0406b1cc2a7f6fe2.tar.bz2 |
sim/or1k: Regenerate sim
This picks up changes for:
- new orfpx64a32 spec
- new unordered instructions
- documentation and symbol updates
sim/ChangeLog:
* or1k/cpu.c: Regenerate.
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate.
Diffstat (limited to 'sim/or1k/model.c')
-rw-r--r-- | sim/or1k/model.c | 1036 |
1 files changed, 1011 insertions, 25 deletions
diff --git a/sim/or1k/model.c b/sim/or1k/model.c index 461ba4b..255023d 100644 --- a/sim/or1k/model.c +++ b/sim/or1k/model.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2019 Free Software Foundation, Inc. +Copyright (C) 1996-2019 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -1603,6 +1603,22 @@ model_or1200_lf_add_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_lf_add_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -1619,6 +1635,22 @@ model_or1200_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_lf_sub_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -1635,6 +1667,22 @@ model_or1200_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_lf_mul_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_lf_div_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -1651,6 +1699,22 @@ model_or1200_lf_div_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_lf_div_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -1667,6 +1731,22 @@ model_or1200_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_lf_rem_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_slli.f @@ -1683,6 +1763,22 @@ model_or1200_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_lf_itof_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_slli.f @@ -1699,7 +1795,151 @@ model_or1200_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200_lf_ftoi_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfeq_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfeq_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfne_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfne_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfge_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfge_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfgt_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfgt_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sflt_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -1715,7 +1955,23 @@ model_or1200_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200_lf_sflt_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfle_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -1731,7 +1987,23 @@ model_or1200_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200_lf_sfle_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfueq_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -1747,7 +2019,23 @@ model_or1200_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200_lf_sfueq_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfune_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -1763,7 +2051,23 @@ model_or1200_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200_lf_sfune_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfugt_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -1779,7 +2083,23 @@ model_or1200_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200_lf_le_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200_lf_sfugt_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfuge_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -1795,6 +2115,118 @@ model_or1200_lf_le_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_lf_sfuge_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfult_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfult_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfule_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfule_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfun_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_lf_sfun_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -1811,6 +2243,22 @@ model_or1200_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_lf_madd_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_empty.f @@ -1827,6 +2275,22 @@ model_or1200_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_lf_cust1_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_l_j (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_j.f @@ -3395,6 +3859,22 @@ model_or1200nd_lf_add_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_lf_add_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -3411,6 +3891,22 @@ model_or1200nd_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_lf_sub_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -3427,6 +3923,22 @@ model_or1200nd_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_lf_mul_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_lf_div_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -3443,6 +3955,22 @@ model_or1200nd_lf_div_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_lf_div_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -3459,6 +3987,22 @@ model_or1200nd_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_lf_rem_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_slli.f @@ -3475,6 +4019,22 @@ model_or1200nd_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_lf_itof_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_slli.f @@ -3491,7 +4051,151 @@ model_or1200nd_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200nd_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200nd_lf_ftoi_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfeq_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfeq_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfne_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfne_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfge_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfge_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfgt_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfgt_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sflt_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -3507,7 +4211,23 @@ model_or1200nd_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200nd_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200nd_lf_sflt_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfle_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -3523,7 +4243,23 @@ model_or1200nd_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200nd_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200nd_lf_sfle_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfueq_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -3539,7 +4275,23 @@ model_or1200nd_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200nd_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200nd_lf_sfueq_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfune_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -3555,7 +4307,23 @@ model_or1200nd_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200nd_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200nd_lf_sfune_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfugt_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -3571,7 +4339,23 @@ model_or1200nd_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200nd_lf_le_s (SIM_CPU *current_cpu, void *sem_arg) +model_or1200nd_lf_sfugt_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfuge_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -3587,6 +4371,118 @@ model_or1200nd_lf_le_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_lf_sfuge_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfult_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfult_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfule_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfule_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfun_s (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_lf_sfun_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -3603,6 +4499,22 @@ model_or1200nd_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_lf_madd_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lf_add_d32.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_empty.f @@ -3618,6 +4530,22 @@ model_or1200nd_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_or1200nd_lf_cust1_d32 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + /* We assume UNIT_NONE == 0 because the tables don't always terminate entries with it. */ @@ -3728,20 +4656,49 @@ static const INSN_TIMING or1200_timing[] = { { OR1K32BF_INSN_L_CUST7, model_or1200_l_cust7, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST8, model_or1200_l_cust8, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_ADD_S, model_or1200_lf_add_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_ADD_D32, model_or1200_lf_add_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_SUB_S, model_or1200_lf_sub_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SUB_D32, model_or1200_lf_sub_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_MUL_S, model_or1200_lf_mul_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_MUL_D32, model_or1200_lf_mul_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_DIV_S, model_or1200_lf_div_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_DIV_D32, model_or1200_lf_div_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_REM_S, model_or1200_lf_rem_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_REM_D32, model_or1200_lf_rem_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_ITOF_S, model_or1200_lf_itof_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_ITOF_D32, model_or1200_lf_itof_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_FTOI_S, model_or1200_lf_ftoi_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_EQ_S, model_or1200_lf_eq_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_NE_S, model_or1200_lf_ne_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_GE_S, model_or1200_lf_ge_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_GT_S, model_or1200_lf_gt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_LT_S, model_or1200_lf_lt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_LE_S, model_or1200_lf_le_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_FTOI_D32, model_or1200_lf_ftoi_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFEQ_S, model_or1200_lf_sfeq_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFEQ_D32, model_or1200_lf_sfeq_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFNE_S, model_or1200_lf_sfne_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFNE_D32, model_or1200_lf_sfne_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFGE_S, model_or1200_lf_sfge_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFGE_D32, model_or1200_lf_sfge_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFGT_S, model_or1200_lf_sfgt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFGT_D32, model_or1200_lf_sfgt_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFLT_S, model_or1200_lf_sflt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFLT_D32, model_or1200_lf_sflt_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFLE_S, model_or1200_lf_sfle_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFLE_D32, model_or1200_lf_sfle_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUEQ_S, model_or1200_lf_sfueq_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUEQ_D32, model_or1200_lf_sfueq_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUNE_S, model_or1200_lf_sfune_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUNE_D32, model_or1200_lf_sfune_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUGT_S, model_or1200_lf_sfugt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUGT_D32, model_or1200_lf_sfugt_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUGE_S, model_or1200_lf_sfuge_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUGE_D32, model_or1200_lf_sfuge_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFULT_S, model_or1200_lf_sfult_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFULT_D32, model_or1200_lf_sfult_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFULE_S, model_or1200_lf_sfule_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFULE_D32, model_or1200_lf_sfule_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUN_S, model_or1200_lf_sfun_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUN_D32, model_or1200_lf_sfun_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_MADD_S, model_or1200_lf_madd_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_MADD_D32, model_or1200_lf_madd_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_CUST1_S, model_or1200_lf_cust1_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_CUST1_D32, model_or1200_lf_cust1_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, }; /* Model timing data for `or1200nd'. */ @@ -3851,20 +4808,49 @@ static const INSN_TIMING or1200nd_timing[] = { { OR1K32BF_INSN_L_CUST7, model_or1200nd_l_cust7, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST8, model_or1200nd_l_cust8, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_ADD_S, model_or1200nd_lf_add_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_ADD_D32, model_or1200nd_lf_add_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_SUB_S, model_or1200nd_lf_sub_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SUB_D32, model_or1200nd_lf_sub_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_MUL_S, model_or1200nd_lf_mul_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_MUL_D32, model_or1200nd_lf_mul_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_DIV_S, model_or1200nd_lf_div_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_DIV_D32, model_or1200nd_lf_div_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_REM_S, model_or1200nd_lf_rem_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_REM_D32, model_or1200nd_lf_rem_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_ITOF_S, model_or1200nd_lf_itof_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_ITOF_D32, model_or1200nd_lf_itof_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_FTOI_S, model_or1200nd_lf_ftoi_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_EQ_S, model_or1200nd_lf_eq_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_NE_S, model_or1200nd_lf_ne_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_GE_S, model_or1200nd_lf_ge_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_GT_S, model_or1200nd_lf_gt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_LT_S, model_or1200nd_lf_lt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_LF_LE_S, model_or1200nd_lf_le_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_FTOI_D32, model_or1200nd_lf_ftoi_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFEQ_S, model_or1200nd_lf_sfeq_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFEQ_D32, model_or1200nd_lf_sfeq_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFNE_S, model_or1200nd_lf_sfne_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFNE_D32, model_or1200nd_lf_sfne_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFGE_S, model_or1200nd_lf_sfge_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFGE_D32, model_or1200nd_lf_sfge_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFGT_S, model_or1200nd_lf_sfgt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFGT_D32, model_or1200nd_lf_sfgt_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFLT_S, model_or1200nd_lf_sflt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFLT_D32, model_or1200nd_lf_sflt_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFLE_S, model_or1200nd_lf_sfle_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFLE_D32, model_or1200nd_lf_sfle_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUEQ_S, model_or1200nd_lf_sfueq_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUEQ_D32, model_or1200nd_lf_sfueq_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUNE_S, model_or1200nd_lf_sfune_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUNE_D32, model_or1200nd_lf_sfune_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUGT_S, model_or1200nd_lf_sfugt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUGT_D32, model_or1200nd_lf_sfugt_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUGE_S, model_or1200nd_lf_sfuge_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUGE_D32, model_or1200nd_lf_sfuge_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFULT_S, model_or1200nd_lf_sfult_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFULT_D32, model_or1200nd_lf_sfult_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFULE_S, model_or1200nd_lf_sfule_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFULE_D32, model_or1200nd_lf_sfule_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUN_S, model_or1200nd_lf_sfun_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_SFUN_D32, model_or1200nd_lf_sfun_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_MADD_S, model_or1200nd_lf_madd_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_MADD_D32, model_or1200nd_lf_madd_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_LF_CUST1_S, model_or1200nd_lf_cust1_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_LF_CUST1_D32, model_or1200nd_lf_cust1_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, }; #endif /* WITH_PROFILE_MODEL_P */ |