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author | Mike Frysinger <vapier@gentoo.org> | 2015-04-16 02:11:12 -0400 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2015-04-17 02:44:30 -0400 |
commit | 034685f9ce92cf6dfb6656745365b6a5904a8e84 (patch) | |
tree | c4b591263048d0a9d89af68c9abd8e69786ed2f7 /sim/mn10300/dv-mn103cpu.c | |
parent | 27b97b40bca216097d16d53fa9408a70cd281479 (diff) | |
download | fsf-binutils-gdb-034685f9ce92cf6dfb6656745365b6a5904a8e84.zip fsf-binutils-gdb-034685f9ce92cf6dfb6656745365b6a5904a8e84.tar.gz fsf-binutils-gdb-034685f9ce92cf6dfb6656745365b6a5904a8e84.tar.bz2 |
sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}
The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET}
except the latter adds a layer of indirection via the sim state. This
lets models set up different functions at runtime and doesn't reach so
directly into the arch-specific cpu state.
It also doesn't make sense to have two sets of macros that do exactly
the same thing, so lets standardize on the one that gets us more.
Diffstat (limited to 'sim/mn10300/dv-mn103cpu.c')
-rw-r--r-- | sim/mn10300/dv-mn103cpu.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/sim/mn10300/dv-mn103cpu.c b/sim/mn10300/dv-mn103cpu.c index e5540ee..e9dd2f6 100644 --- a/sim/mn10300/dv-mn103cpu.c +++ b/sim/mn10300/dv-mn103cpu.c @@ -227,31 +227,31 @@ deliver_mn103cpu_interrupt (struct hw *me, else if (controller->pending_nmi) { controller->pending_nmi = 0; - store_word (SP - 4, CIA_GET (cpu)); + store_word (SP - 4, CPU_PC_GET (cpu)); store_half (SP - 8, PSW); PSW &= ~PSW_IE; SP = SP - 8; - CIA_SET (cpu, 0x40000008); + CPU_PC_SET (cpu, 0x40000008); HW_TRACE ((me, "nmi pc=0x%08lx psw=0x%04x sp=0x%08lx", - (long) CIA_GET (cpu), (unsigned) PSW, (long) SP)); + (long) CPU_PC_GET (cpu), (unsigned) PSW, (long) SP)); } else if ((controller->pending_level < EXTRACT_PSW_LM) && (PSW & PSW_IE)) { /* Don't clear pending level. Request continues to be pending until the interrupt controller clears/changes it */ - store_word (SP - 4, CIA_GET (cpu)); + store_word (SP - 4, CPU_PC_GET (cpu)); store_half (SP - 8, PSW); PSW &= ~PSW_IE; PSW &= ~PSW_LM; PSW |= INSERT_PSW_LM (controller->pending_level); SP = SP - 8; - CIA_SET (cpu, 0x40000000 + controller->interrupt_vector[controller->pending_level]); + CPU_PC_SET (cpu, 0x40000000 + controller->interrupt_vector[controller->pending_level]); HW_TRACE ((me, "port-out ack %d", controller->pending_level)); hw_port_event (me, ACK_PORT, controller->pending_level); HW_TRACE ((me, "int level=%d pc=0x%08lx psw=0x%04x sp=0x%08lx", controller->pending_level, - (long) CIA_GET (cpu), (unsigned) PSW, (long) SP)); + (long) CPU_PC_GET (cpu), (unsigned) PSW, (long) SP)); } if (controller->pending_level < 7) /* FIXME */ |