diff options
| author | Jason Molenda <jmolenda@apple.com> | 1999-12-07 03:56:43 +0000 |
|---|---|---|
| committer | Jason Molenda <jmolenda@apple.com> | 1999-12-07 03:56:43 +0000 |
| commit | c2d11a7da0372ef052af1c74d56e264d8aae4743 (patch) | |
| tree | b2ceadb275bb9a170315ab66111c1f643c9ebf71 /sim/mips | |
| parent | 1e37c28164d4f504b2ae8189d0b82a862cfa323d (diff) | |
| download | fsf-binutils-gdb-c2d11a7da0372ef052af1c74d56e264d8aae4743.zip fsf-binutils-gdb-c2d11a7da0372ef052af1c74d56e264d8aae4743.tar.gz fsf-binutils-gdb-c2d11a7da0372ef052af1c74d56e264d8aae4743.tar.bz2 | |
import gdb-1999-12-06 snapshot
Diffstat (limited to 'sim/mips')
| -rw-r--r-- | sim/mips/ChangeLog | 8 | ||||
| -rw-r--r-- | sim/mips/dv-tx3904sio.c | 5 | ||||
| -rw-r--r-- | sim/mips/interp.c | 3 | ||||
| -rw-r--r-- | sim/mips/mips.igen | 2 |
4 files changed, 15 insertions, 3 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 6c8bc4a..8c3860b 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,11 @@ +1999-11-29 Mark Salter <msalter@cygnus.com> + + * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask + to clear status bits in sdisr register. This is how the hardware works. + + * interp.c (sim_open): Added more memory aliases for jmr3904 hardware + being used by cygmon. + 1999-11-11 Andrew Haley <aph@cygnus.com> * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0 diff --git a/sim/mips/dv-tx3904sio.c b/sim/mips/dv-tx3904sio.c index a1e3ddb..5ba8e37 100644 --- a/sim/mips/dv-tx3904sio.c +++ b/sim/mips/dv-tx3904sio.c @@ -1,6 +1,6 @@ /* This file is part of the program GDB, the GNU debugger. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This program is free software; you can redistribute it and/or modify @@ -167,6 +167,7 @@ struct tx3904sio unsigned_4 sdisr; #define SDISR_WR_MASK 0x00070000U #define SDISR_SET_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8))) +#define SDISR_CLEAR_FLAG_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) & ((b)<< (o)*8))) #define SDISR_GET_TDIS(c) ((c)->sdisr & 0x00020000) #define SDISR_SET_TDIS(c) ((c)->sdisr |= 0x00020000) #define SDISR_GET_RDIS(c) ((c)->sdisr & 0x00010000) @@ -419,7 +420,7 @@ tx3904sio_io_write_buffer (struct hw *me, last_int = controller->sdisr & controller->sdicr; /* HW_TRACE ((me, "sdisr - sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */ - SDISR_SET_BYTE(controller, reg_offset, write_byte); + SDISR_CLEAR_FLAG_BYTE(controller, reg_offset, write_byte); /* HW_TRACE ((me, "sdisr + sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */ next_int = controller->sdisr & controller->sdicr; diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 9c53ff9..a056a01 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -462,8 +462,9 @@ sim_open (kind, cb, abfd, argv) sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x804); /* DRAMC */ - sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */ + sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */ + sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */ diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index be554f5..78998b0 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -3235,6 +3235,7 @@ // MOVF +// MOVT 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf "mov%s<TF> r<RD>, r<RS>, <CC>" *mipsIV: @@ -3246,6 +3247,7 @@ // MOVF.fmt +// MOVT.fmt 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>" *mipsIV: |