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authorAndrew Cagney <cagney@redhat.com>2004-09-24 20:28:24 +0000
committerAndrew Cagney <cagney@redhat.com>2004-09-24 20:28:24 +0000
commitcd62154cc623e47f8d526fd17948f78be64de321 (patch)
tree694c2b3c634fecc3ac870da354314c34a9600341 /sim/mips
parentb96ec7ac6d8385eee134828a87da0eaadfd69fbd (diff)
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2004-09-24 Monika Chaddha <monika@acmet.com>
Committed by Andrew Cagney. * m16.igen (CMP, CMPI): Fix assembler.
Diffstat (limited to 'sim/mips')
-rw-r--r--sim/mips/ChangeLog5
-rw-r--r--sim/mips/m16.igen4
2 files changed, 7 insertions, 2 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 7cf7314..ea4acfb 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+2004-09-24 Monika Chaddha <monika@acmet.com>
+
+ Committed by Andrew Cagney.
+ * m16.igen (CMP, CMPI): Fix assembler.
+
2004-08-18 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
diff --git a/sim/mips/m16.igen b/sim/mips/m16.igen
index 833d7ca..f87a863 100644
--- a/sim/mips/m16.igen
+++ b/sim/mips/m16.igen
@@ -614,7 +614,7 @@
11101,3.RX,3.RY,01010:RR:16::CMP
-"sltiu r<TRX>, r<TRY>"
+"cmp r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
@@ -623,7 +623,7 @@
01110,3.RX,8.IMMED:RI:16::CMPI
-"sltiu r<TRX>, <IMMED>"
+"cmpi r<TRX>, <IMMED>"
*mips16:
*vr4100:
{