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| author | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2022-02-02 11:17:22 +0100 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2022-02-04 19:37:25 -0500 |
| commit | bf484e93483776072291c5cad2e289567d74c818 (patch) | |
| tree | c835425923f43be579228b97ca2b5b0688887e54 /sim/mips | |
| parent | eb06e60a982e3903161252edf8fb8ae0c018c467 (diff) | |
| download | fsf-binutils-gdb-bf484e93483776072291c5cad2e289567d74c818.zip fsf-binutils-gdb-bf484e93483776072291c5cad2e289567d74c818.tar.gz fsf-binutils-gdb-bf484e93483776072291c5cad2e289567d74c818.tar.bz2 | |
sim: Allow toggling of quiet NaN-bit semantics
IEEE754-1985 specifies the top bit of the mantissa as an indicator
of signalling vs. quiet NaN, but does not define the precise semantics.
Most architectures treat this bit as indicating quiet NaN, but legacy
(pre-R6) MIPS goes the other way and treats it as signalling NaN.
This used to be controlled by a macro that was only defined for MIPS.
This patch replaces the macro with a variable to track the current
semantics of the NaN bit and allows differentiation between older
(pre-R6) and and newer MIPS cores.
2022-02-01 Faraz Shahbazker <fshahbazker@wavecomp.com>
sim/common/ChangeLog:
* sim-fpu.c (_sim_fpu): New.
(pack_fpu, unpack_fpu): Allow reversal of quiet NaN semantics.
* sim-fpu.h (sim_fpu_state): New struct.
(_sim_fpu): New extern.
(sim_fpu_quiet_nan_inverted): New define.
sim/mips/ChangeLog:
* cp1.h (fcsr_NAN2008_mask, fcsr_NAN2008_shift): New.
* mips.igen (check_fpu): Select default quiet NaN mode
for legacy MIPS.
* sim-main.h (SIM_QUIET_NAN_NEGATED): Remove.
Diffstat (limited to 'sim/mips')
| -rw-r--r-- | sim/mips/cp1.h | 4 | ||||
| -rw-r--r-- | sim/mips/mips.igen | 3 | ||||
| -rw-r--r-- | sim/mips/sim-main.h | 3 |
3 files changed, 7 insertions, 3 deletions
diff --git a/sim/mips/cp1.h b/sim/mips/cp1.h index 96c51a7..d6d8a88 100644 --- a/sim/mips/cp1.h +++ b/sim/mips/cp1.h @@ -40,6 +40,10 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */ #define fcsr_RM_mask (0x00000003) #define fcsr_RM_shift (0) +/* FCSR bits for IEEE754-2008 compliance. */ +#define fcsr_NAN2008_mask (0x00040000) +#define fcsr_NAN2008_shift (18) + #define fenr_FS (0x00000004) /* Macros to update and retrieve the FCSR condition-code bits. This diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index c5db5c2..b0c5e59 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -5050,6 +5050,9 @@ { if (! COP_Usable (1)) SignalExceptionCoProcessorUnusable (1); + + FCSR &= ~fcsr_NAN2008_mask; + sim_fpu_quiet_nan_inverted = true; } diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index d724688..8e3e85f 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -20,9 +20,6 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */ #ifndef SIM_MAIN_H #define SIM_MAIN_H -/* MIPS uses an unusual format for floating point quiet NaNs. */ -#define SIM_QUIET_NAN_NEGATED - #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) |