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| author | Chris Demetriou <cgd@google.com> | 2004-04-10 07:11:29 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2004-04-10 07:11:29 +0000 |
| commit | 5dbb7b5a1d1498adfae0ff7402eccd5c998efeca (patch) | |
| tree | f1e99970eb1c7c51dacde524be5e76759a0a2478 /sim/mips | |
| parent | 55dc1ac473bb50ec8d11dd76d680459cea10aeb0 (diff) | |
| download | fsf-binutils-gdb-5dbb7b5a1d1498adfae0ff7402eccd5c998efeca.zip fsf-binutils-gdb-5dbb7b5a1d1498adfae0ff7402eccd5c998efeca.tar.gz fsf-binutils-gdb-5dbb7b5a1d1498adfae0ff7402eccd5c998efeca.tar.bz2 | |
im/mips/ChangeLog ]
2004-04-10 Chris Demetriou <cgd@broadcom.com>
* sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
[ sim/testsuite/sim/mips/ChangeLog ]
2004-04-10 Chris Demetriou <cgd@broadcom.com>
* fpu64-ps-sb1.s: New file.
* basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s
if appropriate.
Diffstat (limited to 'sim/mips')
| -rw-r--r-- | sim/mips/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/mips/sb1.igen | 50 |
2 files changed, 54 insertions, 0 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 0c4fd8a..53dc86c 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,7 @@ +2004-04-10 Chris Demetriou <cgd@broadcom.com> + + * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New. + 2004-04-09 Chris Demetriou <cgd@broadcom.com> * mips.igen (check_fmt): Remove. diff --git a/sim/mips/sb1.igen b/sim/mips/sb1.igen index 7a718c7..b6534cb 100644 --- a/sim/mips/sb1.igen +++ b/sim/mips/sb1.igen @@ -192,3 +192,53 @@ check_mdmx_fmtsel (SD_, instruction_0, FMTSEL); StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); } + + +// Paired-Single Extension Instructions +// ------------------------------------ +// +// The SB-1 implements several .PS format instructions that are +// extensions to the MIPS64 architecture. + +010001,10,3.FMT=6,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.PS +"div.%s<FMT> f<FD>, f<FS>, f<FT>" +*sb1: +{ + int fmt = FMT; + check_fpu (SD_); + check_sbx (SD_, instruction_0); + StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); +} + + +010001,10,3.FMT=6,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.PS +"recip.%s<FMT> f<FD>, f<FS>" +*sb1: +{ + int fmt = FMT; + check_fpu (SD_); + check_sbx (SD_, instruction_0); + StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt)); +} + + +010001,10,3.FMT=6,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.PS +"rsqrt.%s<FMT> f<FD>, f<FS>" +*sb1: +{ + int fmt = FMT; + check_fpu (SD_); + check_sbx (SD_, instruction_0); + StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt)); +} + + +010001,10,3.FMT=6,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.PS +"sqrt.%s<FMT> f<FD>, f<FS>" +*sb1: +{ + int fmt = FMT; + check_fpu (SD_); + check_sbx (SD_, instruction_0); + StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt))); +} |