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authorAndrew Cagney <cagney@redhat.com>1998-04-21 04:30:27 +0000
committerAndrew Cagney <cagney@redhat.com>1998-04-21 04:30:27 +0000
commit97f4d183416b7319db0a2c44296e4b677a17d956 (patch)
treeccb6181fe49739f8d9a95d25ac24c3517c3e1007 /sim/mips/mips.igen
parent421cbaae983d05c663270534b65e4fe9dc415dae (diff)
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Implement ERET instruction.
Add {signed,unsigned}_address type.
Diffstat (limited to 'sim/mips/mips.igen')
-rw-r--r--sim/mips/mips.igen20
1 files changed, 20 insertions, 0 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 89c1986..4050a2c 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -349,7 +349,9 @@
*tx19:
// end-sanitize-tx19
{
+ TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
GPR[RT] = GPR[RS] & IMMEDIATE;
+ TRACE_ALU_RESULT (GPR[RT]);
}
@@ -1933,7 +1935,9 @@
*tx19:
// end-sanitize-tx19
{
+ TRACE_ALU_INPUT1 (IMMEDIATE);
GPR[RT] = EXTEND32 (IMMEDIATE << 16);
+ TRACE_ALU_RESULT (GPR[RT]);
}
@@ -5288,6 +5292,20 @@
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
+{
+ if (SR & status_ERL)
+ {
+ /* Oops, not yet available */
+ sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
+ NIA = EPC;
+ SR &= ~status_ERL;
+ }
+ else
+ {
+ NIA = EPC;
+ SR &= ~status_EXL;
+ }
+}
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
@@ -5304,7 +5322,9 @@
*r5900:
// end-sanitize-r5900
{
+ TRACE_ALU_INPUT0 ();
DecodeCoproc (instruction_0);
+ TRACE_ALU_RESULT (GPR[RT]);
}
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0