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authorJason Molenda <jmolenda@apple.com>1999-11-17 02:31:06 +0000
committerJason Molenda <jmolenda@apple.com>1999-11-17 02:31:06 +0000
commit4ce44c668ddc0a909c3f081d98c68bea90a93af9 (patch)
treecf330e250ee02bf77884cb91292faaaa849c5837 /sim/mips/interp.c
parent2daf4fd8960262b76e597427e2e230b3fe6470b3 (diff)
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import gdb-1999-11-16 snapshot
Diffstat (limited to 'sim/mips/interp.c')
-rw-r--r--sim/mips/interp.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 68ffd27..9c53ff9 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -3124,9 +3124,14 @@ decode_coproc (SIM_DESC sd,
CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
ERET Exception return (VR4100 = 01000010000000000000000000011000)
*/
- if (((code == 0x00) || (code == 0x04)) && tail == 0)
+ if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */
+ || (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */
+ && tail == 0)
{
- /* M[TF]C0 - 32 bit word */
+ /* Clear double/single coprocessor move bit. */
+ code &= ~1;
+
+ /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
switch (rd) /* NOTEs: Standard CP0 registers */
{