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authorStephane Carrez <stcarrez@nerim.fr>2002-08-13 08:10:45 +0000
committerStephane Carrez <stcarrez@nerim.fr>2002-08-13 08:10:45 +0000
commitdcceded28ac77cfef16492bf4b3fb3c0e19c0524 (patch)
tree52ed9e5a2ce62a9b20d97eb42a090308baebf440 /sim/m68hc11/interp.c
parentabea9e28ead8f04e13313e749bfdf15d85f0bdbc (diff)
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* interp.c (sim_hw_configure): Connect port-X to cpu-write-port.
* dv-m68hc11.c (m68hc11cpu_ports): Add cpu-write-port input. (m68hc11cpu_port_event): Handle CPU_WRITE_PORT event.
Diffstat (limited to 'sim/m68hc11/interp.c')
-rw-r--r--sim/m68hc11/interp.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c
index 03b6db7..eee7429 100644
--- a/sim/m68hc11/interp.c
+++ b/sim/m68hc11/interp.c
@@ -229,6 +229,10 @@ sim_hw_configure (SIM_DESC sd)
sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
}
+ sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
+ sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
+ sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
+ sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
}
else
@@ -256,6 +260,7 @@ sim_hw_configure (SIM_DESC sd)
/* M68hc11 Timer configuration. */
sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
+ sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
}
/* Create the SPI device. */
@@ -277,6 +282,10 @@ sim_hw_configure (SIM_DESC sd)
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
}
+ sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
+ sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
+ sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
+ sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
}
return 0;