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| author | Tom Tromey <tom@tromey.com> | 2021-04-08 08:52:50 -0600 |
|---|---|---|
| committer | Tom Tromey <tom@tromey.com> | 2021-04-08 14:34:42 -0600 |
| commit | 32a046ab0d7717256f16f59d87438474e825fcb8 (patch) | |
| tree | d3e5a42c96a4c3a4281834210cc91e5f430d2f6e /sim/m32r | |
| parent | 81e6e8ae407b206def2c6840736dad0dcf75eb0b (diff) | |
| download | fsf-binutils-gdb-32a046ab0d7717256f16f59d87438474e825fcb8.zip fsf-binutils-gdb-32a046ab0d7717256f16f59d87438474e825fcb8.tar.gz fsf-binutils-gdb-32a046ab0d7717256f16f59d87438474e825fcb8.tar.bz2 | |
Add system includes in sim
This updates various parts of the sim to include missing system
headers. I made the includes unconditional, because other parts of
the tree are already doing this.
2021-04-08 Tom Tromey <tom@tromey.com>
* traps.c: Include stdlib.h.
* cris-tmpl.c: Include stdlib.h.
sim/erc32/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* func.c: Include sys/time.h.
sim/frv/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* traps.c: Include stdlib.h.
* registers.c: Include stdlib.h.
* profile.c: Include stdlib.h.
* memory.c: Include stdlib.h.
* interrupts.c: Include stdlib.h.
* frv.c: Include stdlib.h.
* cache.c: Include stdlib.h.
sim/iq2000/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* iq2000.c: Include stdlib.h.
sim/m32r/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* traps.c: Include stdlib.h.
* m32r.c: Include stdlib.h.
sim/ppc/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* emul_unix.c: Include time.h.
Diffstat (limited to 'sim/m32r')
| -rw-r--r-- | sim/m32r/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/m32r/m32r.c | 1 | ||||
| -rw-r--r-- | sim/m32r/traps.c | 1 |
3 files changed, 7 insertions, 0 deletions
diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog index f964397..3252bde 100644 --- a/sim/m32r/ChangeLog +++ b/sim/m32r/ChangeLog @@ -1,5 +1,10 @@ 2021-04-08 Tom Tromey <tom@tromey.com> + * traps.c: Include stdlib.h. + * m32r.c: Include stdlib.h. + +2021-04-08 Tom Tromey <tom@tromey.com> + * sim-if.c (sim_open, sim_create_inferior): Use new-style declaration. diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c index 1c5379c..1d0a735 100644 --- a/sim/m32r/m32r.c +++ b/sim/m32r/m32r.c @@ -23,6 +23,7 @@ #include "sim-main.h" #include "cgen-mem.h" #include "cgen-ops.h" +#include <stdlib.h> /* Return the size of REGNO in bytes. */ diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c index 9edf66b..9fca2b1 100644 --- a/sim/m32r/traps.c +++ b/sim/m32r/traps.c @@ -20,6 +20,7 @@ #include "sim-main.h" #include "sim-syscall.h" #include "targ-vals.h" +#include <stdlib.h> #define TRAP_FLUSH_CACHE 12 /* The semantic code invokes this for invalid (unrecognized) instructions. */ |