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author | Mike Frysinger <vapier@gentoo.org> | 2021-05-07 00:26:36 -0400 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2021-05-07 00:34:25 -0400 |
commit | 0ae995e2df001ab7c45c4bc596c4b0b734910c08 (patch) | |
tree | d5dd7809954072111312b2eb027d8571f0263866 /sim/m32c/m32c.opc | |
parent | a5884035977f95b09c28d4bb2276ac4869930e96 (diff) | |
download | fsf-binutils-gdb-0ae995e2df001ab7c45c4bc596c4b0b734910c08.zip fsf-binutils-gdb-0ae995e2df001ab7c45c4bc596c4b0b734910c08.tar.gz fsf-binutils-gdb-0ae995e2df001ab7c45c4bc596c4b0b734910c08.tar.bz2 |
sim: m32c: fix warnings about mixing code & decls
Add scope braces to a bunch of the generated sections to avoid compiler
warnings about mixing code & variable declarations.
Diffstat (limited to 'sim/m32c/m32c.opc')
-rw-r--r-- | sim/m32c/m32c.opc | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/sim/m32c/m32c.opc b/sim/m32c/m32c.opc index efe0495..d19aaf0 100644 --- a/sim/m32c/m32c.opc +++ b/sim/m32c/m32c.opc @@ -1348,12 +1348,14 @@ next_opcode: /** 1101 sss1 ss01 1dst MOVA src,dest */ + { static reg_id map[8] = { r2r0, r3r1, a0, a1 }; prefix (0, 0, 0); sc = decode_src23 (sss, ss, 1); if (!sc.mem || !map[dst]) UNSUPPORTED(); put_reg (map[dst], sc.u.addr); + } /** 0000 0001 1011 ddd0 dd hl 1110 MOVdir R0L,dest */ @@ -1562,6 +1564,7 @@ next_opcode: /** 1000 1110 POPM dest */ + { static int map[] = { r0, r1, r2, r3, a0, a1, sb, fb }; prefix (0, 0, 0); imm = IMM(1); @@ -1580,18 +1583,22 @@ next_opcode: put_reg (map[a], v); put_reg (sp, get_reg (sp) + 4); } + } /** 1010 111w PUSH.size #IMM */ + { + int a; prefix (0, 0, 0); imm = IMM(w+1); tprintf("push%s: %x\n", w ? "hi" : "qi", imm); - int a = get_reg (sp) - 2; + a = get_reg (sp) - 2; if (w) mem_put_hi (a, imm); else mem_put_qi (a, imm); put_reg (sp, a); + } /** 1100 sss w ss00 1110 PUSH.size src */ @@ -1647,6 +1654,7 @@ next_opcode: /** 1000 1111 PUSHM src */ + { static int map[] = { fb, sb, a1, a0, r3, r2, r1, r0 }; imm = IMM(1); tprintf("pushm: %x\n", imm); @@ -1664,6 +1672,7 @@ next_opcode: v = get_reg (map[a]); mem_put_hi (get_reg (sp), v); } + } /** 1001 1110 REIT */ @@ -1676,6 +1685,7 @@ next_opcode: /** 1011 1000 010w 0011 RMPA.size */ + { int count = get_reg (r3); int list1 = get_reg (a0); int list2 = get_reg (a1); @@ -1705,6 +1715,7 @@ next_opcode: put_reg (a1, list2); put_reg (r2r0, (int)(sum & 0xffffffffU)); put_reg (r1, (int)(sum >> 32)); + } /** 1011 ddd w dd10 1110 ROLC.size dest */ |