2003-09-24 Dave Brolley <brolley@redhat.com>

        * profile.h (update_FR_ptime): New prototype.
        (update_FRdouble_ptime): Ditto.
        (update_SPR_ptime): Ditto.
        (increase_ACC_busy): Ditto.
        (enforce_full_acc_latency): Ditto.
        (post_wait_for_SPR): Ditto.
        * profile.c (update_FR_ptime): Moved here from profile-fr500.c.
        (update_FRdouble_ptime): Ditto.
        (update_SPR_ptime): New function.
        (increase_ACC_busy): Ditto.
        (enforce_full_acc_latency): Ditto.
        (vliw_wait_for_fdiv_resource): Correct resource name.
        (vliw_wait_for_fsqrt_resource): Ditto.
        (post_wait_for_SPR): New function.
        * profile-fr500.c (frvbf_model_fr500_u_commit): New function.
        (frvbf_model_fr500_u_gr2fr): Pass out_FRk as output register to
        adjust_float_register_busy.
        (frvbf_model_fr500_u_gr_load): Record latency of SPR registers.
        (frvbf_model_fr500_u_fr_load): Wait for and record latency of SPR
        registers.
        (frvbf_model_fr500_u_float_arith): Ditto.
        (frvbf_model_fr500_u_float_dual_arith): Ditto.
        (frvbf_model_fr500_u_float_div): Ditto.
        (frvbf_model_fr500_u_float_sqrt): Ditto.
        (frvbf_model_fr500_u_float_convert): Ditto.
        (update_FR_ptime): Moved to profile.c
        (update_FRdouble_ptime): Moved to profile.c
        * profile-fr400.c (update_FR_ptime): Removed. Identical to functions
        for other machines.
        (update_FRdouble_ptime): Ditto.
        * arch.h,cpu.h,sem.c,decode.[ch],model.c,sem.c: Regenerated.

1 files changed, 97 insertions, 2 deletions

diff --git a/sim/frv/profile.c b/sim/frv/profile.c
index 6ef1e35..2eadef4 100644
--- a/sim/frv/profile.c
+++ b/sim/frv/profile.c
@@ -1155,6 +1155,52 @@ update_FRdouble_latency_for_load (SIM_CPU *cpu, INT out_FR, int cycles)
 /* Top up the post-processing time of the given FR by the given number of
    cycles.  */
 void
+update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      /* If a load is pending on this register, then add the cycles to
+	 the post processing time for this register. Otherwise apply it
+	 directly to the latency of the register.  */
+      if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR))
+	{
+	  int *fr = ps->fr_latency;
+	  fr[out_FR] += cycles;
+	}
+      else
+	ps->fr_ptime[out_FR] += cycles;
+    }
+}
+
+void
+update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      /* If a load is pending on this register, then add the cycles to
+	 the post processing time for this register. Otherwise apply it
+	 directly to the latency of the register.  */
+      if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR))
+	{
+	  int *fr = ps->fr_latency;
+	  fr[out_FR] += cycles;
+	  if (out_FR < 63)
+	    fr[out_FR + 1] += cycles;
+	}
+      else
+	{
+	  ps->fr_ptime[out_FR] += cycles;
+	  if (out_FR < 63)
+	    ps->fr_ptime[out_FR + 1] += cycles;
+	}
+    }
+}
+
+/* Top up the post-processing time of the given ACC by the given number of
+   cycles.  */
+void
 update_ACC_ptime (SIM_CPU *cpu, INT out_ACC, int cycles)
 {
   if (out_ACC >= 0)
@@ -1167,6 +1213,21 @@ update_ACC_ptime (SIM_CPU *cpu, INT out_ACC, int cycles)
     }
 }
 
+/* Top up the post-processing time of the given SPR by the given number of
+   cycles.  */
+void
+update_SPR_ptime (SIM_CPU *cpu, INT out_SPR, int cycles)
+{
+  if (out_SPR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      /* No load can be pending on this register. Apply the cycles
+	 directly to the latency of the register.  */
+      int *spr = ps->spr_latency;
+      spr[out_SPR] += cycles;
+    }
+}
+
 void
 decrease_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
 {
@@ -1181,6 +1242,26 @@ decrease_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
     }
 }
 
+/* start-sanitize-frv */
+void
+increase_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
+{
+  if (out_ACC >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *acc = ps->acc_busy;
+      acc[out_ACC] += cycles;
+    }
+}
+
+void
+enforce_full_acc_latency (SIM_CPU *cpu, INT in_ACC)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  ps->acc_busy_adjust [in_ACC] = -1;
+}
+
+/* end-sanitize-frv */
 void
 decrease_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles)
 {
@@ -1465,7 +1546,7 @@ vliw_wait_for_fdiv_resource (SIM_CPU *cpu, INT in_resource)
     {
       if (TRACE_INSN_P (cpu))
 	{
-	  sprintf (hazard_name, "Resource hazard for integer division in slot I%d:", in_resource);
+	  sprintf (hazard_name, "Resource hazard for floating point division in slot F%d:", in_resource);
 	}
       ps->vliw_wait = r[in_resource];
     }
@@ -1485,7 +1566,7 @@ vliw_wait_for_fsqrt_resource (SIM_CPU *cpu, INT in_resource)
     {
       if (TRACE_INSN_P (cpu))
 	{
-	  sprintf (hazard_name, "Resource hazard for integer division in slot I%d:", in_resource);
+	  sprintf (hazard_name, "Resource hazard for square root in slot F%d:", in_resource);
 	}
       ps->vliw_wait = r[in_resource];
     }
@@ -1694,6 +1775,20 @@ post_wait_for_CCR (SIM_CPU *cpu, INT in_CCR)
 }
 
 int
+post_wait_for_SPR (SIM_CPU *cpu, INT in_SPR)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *spr = ps->spr_busy;
+
+  if (in_SPR >= 0 && spr[in_SPR] > ps->post_wait)
+    {
+      ps->post_wait = spr[in_SPR];
+      if (TRACE_INSN_P (cpu))
+	sprintf (hazard_name, "Data hazard for spr[%d]:", in_SPR);
+    }
+}
+
+int
 post_wait_for_fdiv (SIM_CPU *cpu, INT slot)
 {
   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);