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| author | Dave Brolley <brolley@redhat.com> | 2003-10-08 18:19:33 +0000 |
|---|---|---|
| committer | Dave Brolley <brolley@redhat.com> | 2003-10-08 18:19:33 +0000 |
| commit | e930b1f54ff2768c5818eb0a450b1d98d46d273d (patch) | |
| tree | beff79b0fd16e78faffe78489d34d064d5618b43 /sim/frv/cache.h | |
| parent | 7c3f9ad027b9ec2906f3367ca7be18e5fb8f6893 (diff) | |
| download | fsf-binutils-gdb-e930b1f54ff2768c5818eb0a450b1d98d46d273d.zip fsf-binutils-gdb-e930b1f54ff2768c5818eb0a450b1d98d46d273d.tar.gz fsf-binutils-gdb-e930b1f54ff2768c5818eb0a450b1d98d46d273d.tar.bz2 | |
2003-10-06 Dave Brolley <brolley@redhat.com>
* profile-fr550.[ch]: New files.
* configure.in: Move frv handling to alphabetically correct placement.
* Makefile.in: Add fr550 support.
* frv-sim.h,frv.c,interrups.c,memory.c,mloop.in,pipeline.c,
profile.[ch],registers.c,traps.c: Add fr550 support.
* arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c:
Regenerate.
Diffstat (limited to 'sim/frv/cache.h')
| -rw-r--r-- | sim/frv/cache.h | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/sim/frv/cache.h b/sim/frv/cache.h index e45ae94..2d17514 100644 --- a/sim/frv/cache.h +++ b/sim/frv/cache.h @@ -1,5 +1,5 @@ /* Cache support for the FRV simulator - Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Copyright (C) 1999, 2000, 2003 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of the GNU Simulators. @@ -165,6 +165,8 @@ typedef struct { */ typedef struct { SIM_CPU *cpu; + unsigned configured_ways; /* Number of ways configured in each set. */ + unsigned configured_sets; /* Number of sets configured in the cache. */ unsigned ways; /* Number of ways in each set. */ unsigned sets; /* Number of sets in the cache. */ unsigned line_size; /* Size of each cache line. */ @@ -200,14 +202,15 @@ typedef struct { #define CACHE_RETURN_DATA(cache, slot, address, mode, N) ( \ T2H_##N (*(mode *)(& (cache)->pipeline[slot].status.return_buffer.data \ - [((address) & ((cache)->line_size - 1) \ - & ~(sizeof (mode) - 1))])) \ + [((address) & ((cache)->line_size - 1))])) \ ) - #define CACHE_RETURN_DATA_ADDRESS(cache, slot, address, N) ( \ ((void *)& (cache)->pipeline[slot].status.return_buffer.data[(address) \ - & ((cache)->line_size - 1) \ - & ~((N) - 1)]) \ + & ((cache)->line_size - 1)]) \ +) + +#define DATA_CROSSES_CACHE_LINE(cache, address, size) ( \ + ((address) & ((cache)->line_size - 1)) + (size) > (cache)->line_size \ ) #define CACHE_INITIALIZED(cache) ((cache)->data_storage != NULL) @@ -217,6 +220,8 @@ void frv_cache_init (SIM_CPU *, FRV_CACHE *); void frv_cache_term (FRV_CACHE *); +void +frv_cache_reconfigure (SIM_CPU *, FRV_CACHE *); int frv_cache_enabled (FRV_CACHE *); |