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| author | Andrew Cagney <cagney@redhat.com> | 2000-04-18 07:55:35 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 2000-04-18 07:55:35 +0000 |
| commit | 27842f65f27045c0f1d7885d4f34ac37625e645c (patch) | |
| tree | ca3d983925949aadbbb5eece5ab9f9327fc3666b /sim/d10v | |
| parent | 5ba474214c1c89d7d3efe4b6d8bc465b9c8c5042 (diff) | |
| download | fsf-binutils-gdb-27842f65f27045c0f1d7885d4f34ac37625e645c.zip fsf-binutils-gdb-27842f65f27045c0f1d7885d4f34ac37625e645c.tar.gz fsf-binutils-gdb-27842f65f27045c0f1d7885d4f34ac37625e645c.tar.bz2 | |
Add support for SIGILL (reserved-instruction-exception).
Diffstat (limited to 'sim/d10v')
| -rw-r--r-- | sim/d10v/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/d10v/interp.c | 9 |
2 files changed, 12 insertions, 2 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index 6d8993a..0b4b1b6 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,8 @@ +Tue Apr 18 16:26:41 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * interp.c (sim_resume): Deliver SIGILL. + (lookup_hash): Do not print SIGILL message. + Tue Feb 22 18:24:56 2000 Andrew Cagney <cagney@b1.cygnus.com> * Makefile.in (SIM_EXTRA_CFLAGS): Define SIM_HAVE_ENVIRONMENT. diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c index 91ebee5..ce4b769 100644 --- a/sim/d10v/interp.c +++ b/sim/d10v/interp.c @@ -99,8 +99,6 @@ lookup_hash (ins, size) { if (h->next == NULL) { - (*d10v_callback->printf_filtered) - (d10v_callback, "ERROR: Illegal instruction %x at PC %x\n", ins, PC); State.exception = SIGILL; State.pc_changed = 1; /* Don't increment the PC. */ return NULL; @@ -979,6 +977,13 @@ sim_resume (sd, step, siggnal) JMP (AE_VECTOR_START); SLOT_FLUSH (); break; + case SIGILL: + SET_BPC (PC); + SET_BPSW (PSW); + SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); + JMP (RIE_VECTOR_START); + SLOT_FLUSH (); + break; default: /* just ignore it */ break; |