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| author | Andrew Cagney <cagney@redhat.com> | 1997-12-03 08:03:33 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-12-03 08:03:33 +0000 |
| commit | aa49c64f3e93a777b3938daac491bbc983f93cf4 (patch) | |
| tree | 22491077b0399a55a1ef41a72d8429d243afbec0 /sim/d10v/ChangeLog | |
| parent | d4b2cc56c066eb021f9873867893f0f408ec8d5d (diff) | |
| download | fsf-binutils-gdb-aa49c64f3e93a777b3938daac491bbc983f93cf4.zip fsf-binutils-gdb-aa49c64f3e93a777b3938daac491bbc983f93cf4.tar.gz fsf-binutils-gdb-aa49c64f3e93a777b3938daac491bbc983f93cf4.tar.bz2 | |
* d10v_sim.h (SEXT56): Define.
* simops.c (OP_4201): For "rac", sign extend 56 bit value before
it is shifted.
* d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using
SIGNED64 macro.
Diffstat (limited to 'sim/d10v/ChangeLog')
| -rw-r--r-- | sim/d10v/ChangeLog | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index 8612dbd..68bca21 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,13 @@ +Wed Dec 3 17:27:06 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d10v_sim.h (SEXT56): Define. + + * simops.c (OP_4201): For "rac", sign extend 56 bit value before + it is shifted. + + * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using + SIGNED64 macro. + Tue Dec 2 15:38:34 1997 Fred Fish <fnf@cygnus.com> * interp.c (sim_resume): Call do_2_short with LEFT_FIRST or |