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| author | Andrew Cagney <cagney@redhat.com> | 1997-10-24 00:52:23 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-10-24 00:52:23 +0000 |
| commit | 1315b4cb60e55c983ca2dac72b239cd9bc72bf9d (patch) | |
| tree | 4f9860c3df86f6007d3886216501e4f24eba6597 /sim/d10v/ChangeLog | |
| parent | cdecdcc4f585e4fd80eccd42f8ae8a8334702dc1 (diff) | |
| download | fsf-binutils-gdb-1315b4cb60e55c983ca2dac72b239cd9bc72bf9d.zip fsf-binutils-gdb-1315b4cb60e55c983ca2dac72b239cd9bc72bf9d.tar.gz fsf-binutils-gdb-1315b4cb60e55c983ca2dac72b239cd9bc72bf9d.tar.bz2 | |
Address MSC compiler issues in d10v_sim.h
Diffstat (limited to 'sim/d10v/ChangeLog')
| -rw-r--r-- | sim/d10v/ChangeLog | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index bee6a0c..21f222e 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,11 @@ +Fri Oct 24 10:26:29 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d10v_sim.h: Include sim-types.h. + (uint8, in816, uiny16, int32, uint32, int64, uint64): Typedef + using unsigned8 et.al. from sim-types.h. + (SEXT32, SEXT40, SEXT44, SEXT60): Replace GCC specific 0x..LL with + SIGNED64 macro. + Wed Oct 22 14:43:00 1997 Andrew Cagney <cagney@b1.cygnus.com> * interp.c (sim_write_phys): New function, write to physical |