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| author | Reuben Thomas <rrt@sc3d.org> | 2022-03-24 12:05:21 +0000 |
|---|---|---|
| committer | Simon Marchi <simon.marchi@efficios.com> | 2022-03-24 10:34:51 -0400 |
| commit | c41524681bf2dad22390fe2b1cfbdeac1576e1e5 (patch) | |
| tree | fba248f858280ed0b4acadaeb0ab93e3c71a23e3 /sim/common/sim-core.h | |
| parent | f1a45585865a724d83133a2299768b5953d2ed94 (diff) | |
| download | fsf-binutils-gdb-c41524681bf2dad22390fe2b1cfbdeac1576e1e5.zip fsf-binutils-gdb-c41524681bf2dad22390fe2b1cfbdeac1576e1e5.tar.gz fsf-binutils-gdb-c41524681bf2dad22390fe2b1cfbdeac1576e1e5.tar.bz2 | |
sim: fix “alligned” typos
Change-Id: Ifd574e38524dd4f1cf0fc003e0c5c7499abc84a0
Diffstat (limited to 'sim/common/sim-core.h')
| -rw-r--r-- | sim/common/sim-core.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/common/sim-core.h b/sim/common/sim-core.h index 5f152ee..df4e3e1 100644 --- a/sim/common/sim-core.h +++ b/sim/common/sim-core.h @@ -248,7 +248,7 @@ extern void *sim_core_trans_addr order (including xor endian). Should the transfer fail, the operation shall abort (no return). - ALIGNED assumes yhat the specified ADDRESS is correctly alligned + ALIGNED assumes that the specified ADDRESS is correctly aligned for an N byte transfer (no alignment checks are made). Passing an incorrectly aligned ADDRESS is erroneous. @@ -256,7 +256,7 @@ extern void *sim_core_trans_addr of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being taken should the check fail. - MISSALIGNED transfers the data regardless. + MISALIGNED transfers the data regardless. Misaligned xor-endian accesses are broken into a sequence of transfers each <= WITH_XOR_ENDIAN bytes */ |