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authorMike Frysinger <vapier@gentoo.org>2011-03-06 00:20:21 +0000
committerMike Frysinger <vapier@gentoo.org>2011-03-06 00:20:21 +0000
commitef016f835f292f01f065412fcfd84c50bfff1fea (patch)
treefe72facf7bcdc58af74f3a37d30f0f25d501f6a0 /sim/bfin/dv-bfin_spi.h
parent7dcf22fd41de725f3280c80a1274bcef309d6891 (diff)
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sim: bfin: new port
This can boot Das U-Boot and a Linux kernel. It also supports Linux userspace FLAT and FDPIC (dynamic and static) ELFs. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim/bfin/dv-bfin_spi.h')
-rw-r--r--sim/bfin/dv-bfin_spi.h54
1 files changed, 54 insertions, 0 deletions
diff --git a/sim/bfin/dv-bfin_spi.h b/sim/bfin/dv-bfin_spi.h
new file mode 100644
index 0000000..5e216bf
--- /dev/null
+++ b/sim/bfin/dv-bfin_spi.h
@@ -0,0 +1,54 @@
+/* Blackfin Serial Peripheral Interface (SPI) model
+
+ Copyright (C) 2010-2011 Free Software Foundation, Inc.
+ Contributed by Analog Devices, Inc.
+
+ This file is part of simulators.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef DV_BFIN_SPI_H
+#define DV_BFIN_SPI_H
+
+/* XXX: This should be pushed into the model data. */
+#define BFIN_MMR_SPI_SIZE (4 * 7)
+
+/* SPI_CTL Masks. */
+#define TIMOD (3 << 0)
+#define RDBR_CORE (0 << 0)
+#define TDBR_CORE (1 << 0)
+#define RDBR_DMA (2 << 0)
+#define TDBR_DMA (3 << 0)
+#define SZ (1 << 2)
+#define GM (1 << 3)
+#define PSSE (1 << 4)
+#define EMISO (1 << 5)
+#define SZE (1 << 8)
+#define LSBF (1 << 9)
+#define CPHA (1 << 10)
+#define CPOL (1 << 11)
+#define MSTR (1 << 12)
+#define WOM (1 << 13)
+#define SPE (1 << 14)
+
+/* SPI_STAT Masks. */
+#define SPIF (1 << 0)
+#define MODF (1 << 1)
+#define TXE (1 << 2)
+#define TXS (1 << 3)
+#define RBSY (1 << 4)
+#define RXS (1 << 5)
+#define TXCOL (1 << 6)
+
+#endif