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| author | Mike Frysinger <vapier@gentoo.org> | 2011-03-29 01:41:49 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-03-29 01:41:49 +0000 |
| commit | 1a3af0bfc3b53c392923b62275c9ca72bee46f7b (patch) | |
| tree | 2b361ef14e07d47c408ad814b1a9e84376ae4539 /sim/bfin/bfin-sim.c | |
| parent | f4a2f576d439afac300134257b3d9fcfc7e15fd3 (diff) | |
| download | fsf-binutils-gdb-1a3af0bfc3b53c392923b62275c9ca72bee46f7b.zip fsf-binutils-gdb-1a3af0bfc3b53c392923b62275c9ca72bee46f7b.tar.gz fsf-binutils-gdb-1a3af0bfc3b53c392923b62275c9ca72bee46f7b.tar.bz2 | |
sim: bfin: fix sign extension with 16bit acc add insns
The current implementation attempts to handle the 16bit sign extension
itself. Unfortunately, it gets it right in some cases. So rather than
fix that logic, just drop it in favor of using 16bit signed casts. Now
gcc will take care of getting the logic right.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim/bfin/bfin-sim.c')
| -rw-r--r-- | sim/bfin/bfin-sim.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index 1555dc2..27112c6 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -4523,23 +4523,16 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) } else if (aop == 1 && aopcde == 12) { - bu32 val0 = ((AWREG (0) >> 16) + (AWREG (0) & 0xFFFF)) & 0xFFFF; - bu32 val1 = ((AWREG (1) >> 16) + (AWREG (1) & 0xFFFF)) & 0xFFFF; + bs32 val0 = (bs16)(AWREG (0) >> 16) + (bs16)AWREG (0); + bs32 val1 = (bs16)(AWREG (1) >> 16) + (bs16)AWREG (1); TRACE_INSN (cpu, "R%i = A1.L + A1.H, R%i = A0.L + A0.H;", dst1, dst0); if (dst0 == dst1) illegal_instruction_combination (cpu); - if (val0 & 0x8000) - val0 |= 0xFFFF0000; - - if (val1 & 0x8000) - val1 |= 0xFFFF0000; - SET_DREG (dst0, val0); SET_DREG (dst1, val1); - /* XXX: ASTAT ? */ } else if (aopcde == 1) { |