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| author | Mike Frysinger <vapier@gentoo.org> | 2011-03-26 06:02:41 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-03-26 06:02:41 +0000 |
| commit | fcd1ee07d35e970766622ea09e79a9b80c632cf9 (patch) | |
| tree | 3de69cc7320cca78c6161d015fb7e7e6f3460958 /sim/bfin/bfin-sim.c | |
| parent | 81723326fe1126b9dfd48e99b65ba52e333ede58 (diff) | |
| download | fsf-binutils-gdb-fcd1ee07d35e970766622ea09e79a9b80c632cf9.zip fsf-binutils-gdb-fcd1ee07d35e970766622ea09e79a9b80c632cf9.tar.gz fsf-binutils-gdb-fcd1ee07d35e970766622ea09e79a9b80c632cf9.tar.bz2 | |
sim: bfin: add missing VS set with add/sub insns
The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim/bfin/bfin-sim.c')
| -rw-r--r-- | sim/bfin/bfin-sim.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index 467d742..7e747ff 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -4122,6 +4122,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) SET_ASTATREG (ac0, ac0_i); SET_ASTATREG (v, v_i); + if (v_i) + SET_ASTATREG (vs, v_i); + if (HL) SET_DREG_H (dst0, val << 16); else |