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| author | Jim Wilson <jim.wilson@linaro.org> | 2017-02-14 15:23:12 -0800 |
|---|---|---|
| committer | Jim Wilson <jim.wilson@linaro.org> | 2017-02-14 15:23:12 -0800 |
| commit | 742e3a7781c7f29136ccc36673ef2c887ba2860d (patch) | |
| tree | 7316aaa13056b55e389b135a32e903fcacfb4aa5 /sim/aarch64/ChangeLog | |
| parent | bf25e9a0f1315829defcb6ef36d8fef9d370e822 (diff) | |
| download | fsf-binutils-gdb-742e3a7781c7f29136ccc36673ef2c887ba2860d.zip fsf-binutils-gdb-742e3a7781c7f29136ccc36673ef2c887ba2860d.tar.gz fsf-binutils-gdb-742e3a7781c7f29136ccc36673ef2c887ba2860d.tar.bz2 | |
Add self to aarch64 maintainers. Fix mla instruction.
sim/
* MAINTAINTERS (aarch64): Add myself.
sim/aarch64/
* simulator.c (do_vec_MLA): Rewrite switch body.
sim/testsuite/sim/aarch64/
* mla.s: New.
Diffstat (limited to 'sim/aarch64/ChangeLog')
| -rw-r--r-- | sim/aarch64/ChangeLog | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index 7d00621..e8d66a6 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,5 +1,7 @@ 2017-02-14 Jim Wilson <jim.wilson@linaro.org> + * simulator.c (do_vec_MLA): Rewrite switch body. + * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and 2. Move test_false if inside loop. Fix logic for computing result stored to vd. |