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| author | Jim Wilson <jim.wilson@linaro.org> | 2017-01-17 16:01:40 -0800 |
|---|---|---|
| committer | Jim Wilson <jim.wilson@linaro.org> | 2017-01-17 16:11:09 -0800 |
| commit | 05b3d79d265aa9de2a81ac2d0f5e6f5821161f34 (patch) | |
| tree | e6e003e2f85da81fdc73ee6a4b209170a2ada370 /sim/aarch64/ChangeLog | |
| parent | 11741d50eff1424bb1f628ede3dfe42a74343b52 (diff) | |
| download | fsf-binutils-gdb-05b3d79d265aa9de2a81ac2d0f5e6f5821161f34.zip fsf-binutils-gdb-05b3d79d265aa9de2a81ac2d0f5e6f5821161f34.tar.gz fsf-binutils-gdb-05b3d79d265aa9de2a81ac2d0f5e6f5821161f34.tar.bz2 | |
Fixes for addv and xtn2 instructions.
sim/aarch64/
* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
case 3, call HALT_UNALLOC unconditionally.
(do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
i + 2. Delete if on bias, change index to i + bias * X.
sim/testsuite/sim/aarch64/
* addv.s: New.
* xtn.s: New.
Diffstat (limited to 'sim/aarch64/ChangeLog')
| -rw-r--r-- | sim/aarch64/ChangeLog | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index 814365d..d9dd4f6 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,3 +1,11 @@ +2017-01-17 Jim Wilson <jim.wilson@linaro.org> + + * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of + aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In + case 3, call HALT_UNALLOC unconditionally. + (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to + i + 2. Delete if on bias, change index to i + bias * X. + 2017-01-09 Jim Wilson <jim.wilson@linaro.org> * simulator.c (do_vec_UZP): Rewrite. |