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| author | Jim Wilson <jim.wilson@linaro.org> | 2017-02-14 14:35:57 -0800 |
|---|---|---|
| committer | Jim Wilson <jim.wilson@linaro.org> | 2017-02-14 14:35:57 -0800 |
| commit | bf25e9a0f1315829defcb6ef36d8fef9d370e822 (patch) | |
| tree | b93f63bfa8ab4f2ddf4678d76d5630c63bfd05b2 /sim/aarch64/ChangeLog | |
| parent | e8f42b5e36b2083e36855007442aff110291b6aa (diff) | |
| download | fsf-binutils-gdb-bf25e9a0f1315829defcb6ef36d8fef9d370e822.zip fsf-binutils-gdb-bf25e9a0f1315829defcb6ef36d8fef9d370e822.tar.gz fsf-binutils-gdb-bf25e9a0f1315829defcb6ef36d8fef9d370e822.tar.bz2 | |
Fix bit/bif instructions.
sim/aarch64/
* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
2. Move test_false if inside loop. Fix logic for computing result
stored to vd.
sim/testsuite/sim/aarch64
* bit.s: New.
Diffstat (limited to 'sim/aarch64/ChangeLog')
| -rw-r--r-- | sim/aarch64/ChangeLog | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index 2a21fc3..7d00621 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,5 +1,9 @@ 2017-02-14 Jim Wilson <jim.wilson@linaro.org> + * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and + 2. Move test_false if inside loop. Fix logic for computing result + stored to vd. + * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. (do_vec_LDn_single, do_vec_STn_single): New. (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with |