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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-07-02 10:51:09 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2019-07-02 10:51:09 +0100 |
| commit | 83adff695c522df8259e421162e194a95713eb45 (patch) | |
| tree | 59f40754a57cd7e542ef491bcb2143bc644770af /readline | |
| parent | 8941884429c305ad42a41f759a98c8cca4d4aacc (diff) | |
| download | fsf-binutils-gdb-83adff695c522df8259e421162e194a95713eb45.zip fsf-binutils-gdb-83adff695c522df8259e421162e194a95713eb45.tar.gz fsf-binutils-gdb-83adff695c522df8259e421162e194a95713eb45.tar.bz2 | |
[AArch64] Add missing C_MAX_ELEM flags for SVE conversions
SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.
Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
gas/
* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
SCVTF, UCVTF, LSR and ASR.
* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
Diffstat (limited to 'readline')
0 files changed, 0 insertions, 0 deletions