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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-01-11 19:14:02 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-03-18 15:32:16 +0800 |
| commit | 3b374308d3006407b9571e573e4ccce4e904a4c4 (patch) | |
| tree | 96bfce86a830f793e0ef73924c4b3c1b3788b68a /opcodes | |
| parent | 5fac3f02edacfca458f7eeaaaa33a87e26e0e332 (diff) | |
| download | fsf-binutils-gdb-3b374308d3006407b9571e573e4ccce4e904a4c4.zip fsf-binutils-gdb-3b374308d3006407b9571e573e4ccce4e904a4c4.tar.gz fsf-binutils-gdb-3b374308d3006407b9571e573e4ccce4e904a4c4.tar.bz2 | |
RISC-V: Prefetch hint instructions and operand set
This commit adds 'Zicbop' hint instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction class.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add handling for new operand
type 'f' (32-byte aligned pseudo S-type immediate for prefetch
hints).
(validate_riscv_insn): Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
MASK_PREFETCH_W): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class INSN_CLASS_ZICBOP.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add handling for new operand
type.
* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-dis.c | 4 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 3 |
2 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 34724d4..57b798d 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -424,6 +424,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); break; + case 'f': + print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); + break; + case 'a': info->target = EXTRACT_JTYPE_IMM (l) + pc; (*info->print_address_func) (info->target, info); diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 00ee21d..6a28898 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -388,6 +388,9 @@ const struct riscv_opcode riscv_opcodes[] = {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS }, +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, {"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 }, {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, |