[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field

The internal CN register representation for coprocessor fields used in aarch64
sys, sysl instructions are removed in this patch.

After the change, those fields are represented as immediate. Related checks are
added as well.

opcodes/

	* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
	qualifier.
	(operand_general_constraint_met_p): Remove case for CP_REG.
	(aarch64_print_operand): Print CRn, CRm operand using imm field.
	* aarch64-tbl.h (QL_SYS): Use CR qualifier.
	(QL_SYSL): Likewise.
	(aarch64_opcode_table): Change CRn, CRm operand class and type.
	* aarch64-opc-2.c : Regenerate.
	* aarch64-asm-2.c : Likewise.
	* aarch64-dis-2.c : Likewise.

include/

	* opcode/aarch64.h (aarch64_operand_class): Remove
	AARCH64_OPND_CLASS_CP_REG.
	(enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
	AARCH64_OPND_Cm to AARCH64_OPND_CRm.
	(aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.

gas/

	* config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register.
	(get_reg_expected_msg): Remove CN register case.
	(parse_operands): rewrite parser for CRn, CRm operand.
	(reg_names): Remove CN register.
	* testsuite/gas/aarch64/diagnostic.s: Add a new test case.
	* testsuite/gas/aarch64/diagnostic.l: Adjust error message.

6 files changed, 29 insertions, 25 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2f5c6c9..34eb768 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,16 @@
+2016-12-13 Renlin Li <renlin.li@arm.com>
+
+	* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
+	qualifier.
+	(operand_general_constraint_met_p): Remove case for CP_REG.
+	(aarch64_print_operand): Print CRn, CRm operand using imm field.
+	* aarch64-tbl.h (QL_SYS): Use CR qualifier.
+	(QL_SYSL): Likewise.
+	(aarch64_opcode_table): Change CRn, CRm operand class and type.
+	* aarch64-opc-2.c : Regenerate.
+	* aarch64-asm-2.c : Likewise.
+	* aarch64-dis-2.c : Likewise.
+
 2016-12-12  Yao Qi  <yao.qi@linaro.org>
 
 	* rx-dis.c: Include <setjmp.h>
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 121bde8..5d5ec78 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -611,8 +611,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 26:
     case 27:
     case 28:
-    case 36:
-    case 37:
     case 144:
     case 145:
     case 146:
@@ -653,6 +651,8 @@ aarch64_insert_operand (const aarch64_operand *self,
       return aarch64_ins_ldst_reglist_r (self, info, code, inst);
     case 35:
       return aarch64_ins_ldst_elemlist (self, info, code, inst);
+    case 36:
+    case 37:
     case 38:
     case 48:
     case 49:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 19b3dcf..ffae39e 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -18694,8 +18694,6 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 26:
     case 27:
     case 28:
-    case 36:
-    case 37:
     case 144:
     case 145:
     case 146:
@@ -18740,6 +18738,8 @@ aarch64_extract_operand (const aarch64_operand *self,
       return aarch64_ext_ldst_reglist_r (self, info, code, inst);
     case 35:
       return aarch64_ext_ldst_elemlist (self, info, code, inst);
+    case 36:
+    case 37:
     case 38:
     case 48:
     case 49:
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index e1729a8..cfa7467 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -60,8 +60,8 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
   {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
   {AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"},
-  {AARCH64_OPND_CLASS_CP_REG, "Cn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
-  {AARCH64_OPND_CLASS_CP_REG, "Cm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 5b9eb27..4275d4d 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -711,6 +711,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] =
      First 3 fields:
      Lower bound, higher bound, unused.  */
 
+  {0, 15, 0, "CR",       OQK_VALUE_IN_RANGE},
   {0,  7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
   {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
   {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
@@ -2418,16 +2419,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	}
       break;
 
-    case AARCH64_OPND_CLASS_CP_REG:
-      /* Cn or Cm: 4-bit opcode field named for historical reasons.
-	 valid range: C0 - C15.  */
-      if (opnd->reg.regno > 15)
-	{
-	  set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
-	  return 0;
-	}
-      break;
-
     case AARCH64_OPND_CLASS_SYSTEM:
       switch (type)
 	{
@@ -3187,9 +3178,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 		opnd->reglane.index);
       break;
 
-    case AARCH64_OPND_Cn:
-    case AARCH64_OPND_Cm:
-      snprintf (buf, size, "C%d", opnd->reg.regno);
+    case AARCH64_OPND_CRn:
+    case AARCH64_OPND_CRm:
+      snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
       break;
 
     case AARCH64_OPND_IDX:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 0efd98e..4fd009f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -59,13 +59,13 @@
 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}.  */
 #define QL_SYS			\
 {				\
-  QLF5(NIL,NIL,NIL,NIL,X),	\
+  QLF5(NIL,CR,CR,NIL,X),	\
 }
 
 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>.  */
 #define QL_SYSL			\
 {				\
-  QLF5(X,NIL,NIL,NIL,NIL),	\
+  QLF5(X,NIL,CR,CR,NIL),	\
 }
 
 /* e.g. ADRP <Xd>, <label>.  */
@@ -3237,13 +3237,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0),
   CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0),
   CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, 0, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
-  CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, Cn, Cm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)),
+  CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)),
   CORE_INSN ("at",  0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS),
   CORE_INSN ("dc",  0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),
   CORE_INSN ("ic",  0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
   CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
   CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, 0),
-  CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0),
+  CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
   CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, 0),
   V8_3_INSN ("paciaz",  0xd503231f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
   V8_3_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
@@ -4084,9 +4084,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
       "a SIMD vector register list")					\
     Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(),			\
       "a SIMD vector element list")					\
-    Y(CP_REG, regno, "Cn", 0, F(FLD_CRn),				\
+    Y(IMMEDIATE, imm, "CRn", 0, F(FLD_CRn),				\
       "a 4-bit opcode field named for historical reasons C0 - C15")	\
-    Y(CP_REG, regno, "Cm", 0, F(FLD_CRm),				\
+    Y(IMMEDIATE, imm, "CRm", 0, F(FLD_CRm),				\
       "a 4-bit opcode field named for historical reasons C0 - C15")	\
     Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4),				\
       "an immediate as the index of the least significant byte")	\