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| author | Maciej W. Rozycki <macro@linux-mips.org> | 2011-11-16 12:24:08 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@linux-mips.org> | 2011-11-16 12:24:08 +0000 |
| commit | 514f48bb1dbccb1c3820236b8dbc11b64c155984 (patch) | |
| tree | ebf66000411452636ac62bcb17fc3db0a43e559e /opcodes | |
| parent | 7a795ef4a7385b934b780c35c482c4b7c7f96a44 (diff) | |
| download | fsf-binutils-gdb-514f48bb1dbccb1c3820236b8dbc11b64c155984.zip fsf-binutils-gdb-514f48bb1dbccb1c3820236b8dbc11b64c155984.tar.gz fsf-binutils-gdb-514f48bb1dbccb1c3820236b8dbc11b64c155984.tar.bz2 | |
* micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
for "alnv.ps".
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/micromips-opc.c | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 06ff024..eab8c0a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2011-11-16 Maciej W. Rozycki <macro@codesourcery.com> + + * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP + for "alnv.ps". + 2011-11-02 Nick Clifton <nickc@redhat.com> * po/it.po: New Italian translation. diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index 852081e..251d801 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -167,9 +167,9 @@ const struct mips_opcode micromips_opcodes[] = {"addu", "md,me,ml", 0x0400, 0xfc01, 0, WR_md|RD_me|RD_ml, I1 }, {"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, -/* We have no flag to mark the read from "y", so we use TRAP to disable +/* We have no flag to mark the read from "y", so we use NODS to disable delay slot scheduling of ALNV.PS altogether. */ -{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, TRAP|WR_D|RD_S|RD_T|FP_D, 0, I1 }, +{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, NODS|WR_D|RD_S|RD_T|FP_D, 0, I1 }, {"and", "mf,mt,mg", 0x4480, 0xffc0, 0, WR_mf|RD_mf|RD_mg, I1 }, {"and", "mf,mg,mx", 0x4480, 0xffc0, 0, WR_mf|RD_mf|RD_mg, I1 }, {"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |