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| author | Dmitry Selyutin <ghostmansd@gmail.com> | 2022-07-25 16:10:14 +0300 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2022-08-11 18:38:29 +0930 |
| commit | 33ae8a3ae31d8ea787d79d2a677d960721ffe682 (patch) | |
| tree | 6af5ac519b400849a6f7f3e4dc1f2e6df2a8c5dc /opcodes | |
| parent | df4860daad8ffa29e0185e543a0a2aae32f7a925 (diff) | |
| download | fsf-binutils-gdb-33ae8a3ae31d8ea787d79d2a677d960721ffe682.zip fsf-binutils-gdb-33ae8a3ae31d8ea787d79d2a677d960721ffe682.tar.gz fsf-binutils-gdb-33ae8a3ae31d8ea787d79d2a677d960721ffe682.tar.bz2 | |
ppc/svp64: support LibreSOC architecture
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
For more details, visit https://libre-soc.org.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ppc-dis.c | 5 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 17 |
2 files changed, 14 insertions, 8 deletions
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 7c7dde8..db03dce 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = { | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 0 }, + { "libresoc",(PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 + | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 + | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 + | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64), + 0 }, { "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 7637d3e..7ad5803 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4819,19 +4819,20 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define PPCEFS2 PPC_OPCODE_EFS2 #define PPCBRLK PPC_OPCODE_BRLOCK #define PPCPMR PPC_OPCODE_PMR -#define PPCTMR PPC_OPCODE_TMR +#define PPCTMR PPC_OPCODE_TMR #define PPCCHLK PPC_OPCODE_CACHELCK #define PPCRFMCI PPC_OPCODE_RFMCI -#define E500MC PPC_OPCODE_E500MC +#define E500MC PPC_OPCODE_E500MC #define PPCA2 PPC_OPCODE_A2 -#define TITAN PPC_OPCODE_TITAN -#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN +#define TITAN PPC_OPCODE_TITAN +#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN #define E500 PPC_OPCODE_E500 #define E6500 PPC_OPCODE_E6500 -#define PPCVLE PPC_OPCODE_VLE -#define PPCHTM PPC_OPCODE_POWER8 -#define E200Z4 PPC_OPCODE_E200Z4 -#define PPCLSP PPC_OPCODE_LSP +#define PPCVLE PPC_OPCODE_VLE +#define PPCHTM PPC_OPCODE_POWER8 +#define E200Z4 PPC_OPCODE_E200Z4 +#define PPCLSP PPC_OPCODE_LSP +#define SVP64 PPC_OPCODE_SVP64 /* Used to mark extended mnemonic in deprecated field so that -Mraw won't use this variant in disassembly. */ #define EXT PPC_OPCODE_RAW |