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| author | Alan Modra <amodra@gmail.com> | 2014-06-07 12:09:04 +0930 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2014-06-07 14:55:11 +0930 |
| commit | a47622ac1badbd906c7533ef6011b6bb021271ee (patch) | |
| tree | 3e6ad4e4cb4ed80e652cf756cbbacf4a7a6ae3d1 /opcodes | |
| parent | d634c69f87e9b88a5ff5cd8af7a1f60e738ea0bd (diff) | |
| download | fsf-binutils-gdb-a47622ac1badbd906c7533ef6011b6bb021271ee.zip fsf-binutils-gdb-a47622ac1badbd906c7533ef6011b6bb021271ee.tar.gz fsf-binutils-gdb-a47622ac1badbd906c7533ef6011b6bb021271ee.tar.bz2 | |
Allow both signed and unsigned fields in PowerPC cmpli insn
There are legitimate reasons to allow a signed value in a cmpli insn
field, for example to test for a "stw r1,lock@sdarel(r13)" instruction
in user code, a kernel might use
subis r3,r3,STW_R1_0R13@ha # subtract off high part
cmplwi r3,lock@sdarel # is low part accessing lock?
Since the lock@sdarel may take a range of -32768 to 32767,
the allowed range of cmpli immediate must be at least [-32768,65535].
bfd/
* elf32-ppc.c (ppc_elf_relocate_section): Treat field of cmpli
insn as a bitfield; Use complain_overflow_bitfield.
* elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
opcodes/
* ppc-opc.c (UISIGNOPT): Define and use with cmpli.
gas/
* config/tc-ppc.c (ppc_insert_operand): Handle PPC_OPERAND_SIGNOPT
on unsigned fields. Comment on PPC_OPERAND_SIGNOPT signed fields
in 64-bit mode.
gold/
* powerpc.cc (relocate): Treat field of cmpli insn as a bitfield.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 13 |
2 files changed, 12 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 499ec64..6e3d6c9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2014-06-07 Alan Modra <amodra@gmail.com> + + * ppc-opc.c (UISIGNOPT): Define and use with cmpli. + 2014-06-05 Joel Brobecker <brobecker@adacore.com> * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 1d27961..a5cfe1a 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -654,8 +654,11 @@ const struct powerpc_operand powerpc_operands[] = #define UI TO + 1 { 0xffff, 0, NULL, NULL, 0 }, +#define UISIGNOPT UI + 1 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT }, + /* The IMM field in an SE_IM5 instruction. */ -#define UI5 UI + 1 +#define UI5 UISIGNOPT + 1 { 0x1f, 4, NULL, NULL, 0 }, /* The OIMM field in an SE_OIM5 instruction. */ @@ -3500,10 +3503,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}}, -{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}}, -{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}}, -{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}}, -{"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}}, +{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UISIGNOPT}}, +{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UISIGNOPT}}, +{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UISIGNOPT}}, +{"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UISIGNOPT}}, {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}}, {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}}, |