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authorRichard Sandiford <rdsandiford@googlemail.com>2014-03-04 21:16:38 +0000
committerRichard Sandiford <rdsandiford@googlemail.com>2014-03-04 21:16:38 +0000
commit079b5aec63d98106d75981c48ec5191343853986 (patch)
tree2eb00efcd9472b342d6301a1f47da6a46a9328cc /opcodes
parent0b55a33ebe733e0c7cc955db8caa280a8184c607 (diff)
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opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the udi* instructions so that they come after the Loongson extensions.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/mips-opc.c132
2 files changed, 71 insertions, 66 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 43d0cb3..ea74ba6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
+ so that they come after the Loongson extensions.
+
2014-03-03 Alan Modra <amodra@gmail.com>
* i386-gen.c (process_copyright): Emit copyright notice on one line.
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index fd619f4..dfd3c35 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1956,72 +1956,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"zcb", "(b)", 0x7000071f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
{"zcbt", "(b)", 0x7000075f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
-/* User Defined Instruction. */
-{"udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi0", "s,+3", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi0", "+4", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi1", "s,t,d,+1", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi1", "s,+3", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi1", "+4", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi2", "s,t,d,+1", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi2", "s,+3", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi2", "+4", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi3", "s,t,d,+1", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi3", "s,+3", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi3", "+4", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi4", "s,t,d,+1", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi4", "s,+3", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi4", "+4", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi5", "s,t,d,+1", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi5", "s,+3", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi5", "+4", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi6", "s,t,d,+1", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi6", "s,+3", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi6", "+4", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi7", "s,t,d,+1", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi7", "s,+3", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi7", "+4", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi8", "s,t,d,+1", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi8", "s,+3", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi8", "+4", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi9", "s,t,d,+1", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi9", "s,+3", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi9", "+4", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi10", "s,t,d,+1", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi10", "s,+3", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi10", "+4", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi11", "s,t,d,+1", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi11", "s,+3", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi11", "+4", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi12", "s,t,d,+1", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi12", "s,+3", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi12", "+4", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi13", "s,t,d,+1", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi13", "s,+3", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi13", "+4", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi14", "s,t,d,+1", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi14", "s,+3", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi14", "+4", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi15", "s,t,d,+1", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi15", "s,+3", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi15", "+4", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
-
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 },
@@ -3103,6 +3037,72 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"move.v", "+d,+e", 0x78be0019, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
{"lsa", "d,v,t,+~", 0x00000005, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
{"dlsa", "d,v,t,+~", 0x00000015, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA64, 0 },
+
+/* User Defined Instruction. */
+{"udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi0", "s,+3", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi0", "+4", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi1", "s,t,d,+1", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi1", "s,+3", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi1", "+4", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi2", "s,t,d,+1", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi2", "s,+3", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi2", "+4", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi3", "s,t,d,+1", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi3", "s,+3", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi3", "+4", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi4", "s,t,d,+1", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi4", "s,+3", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi4", "+4", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi5", "s,t,d,+1", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi5", "s,+3", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi5", "+4", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi6", "s,t,d,+1", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi6", "s,+3", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi6", "+4", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi7", "s,t,d,+1", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi7", "s,+3", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi7", "+4", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi8", "s,t,d,+1", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi8", "s,+3", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi8", "+4", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi9", "s,t,d,+1", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi9", "s,+3", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi9", "+4", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi10", "s,t,d,+1", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi10", "s,+3", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi10", "+4", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi11", "s,t,d,+1", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi11", "s,+3", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi11", "+4", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi12", "s,t,d,+1", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi12", "s,+3", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi12", "+4", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi13", "s,t,d,+1", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi13", "s,+3", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi13", "+4", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi14", "s,t,d,+1", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi14", "s,+3", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi14", "+4", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi15", "s,t,d,+1", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi15", "s,+3", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi15", "+4", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the