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| author | Nick Clifton <nickc@redhat.com> | 2015-11-02 14:14:22 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2015-11-02 14:14:22 +0000 |
| commit | e292aa7a9529771c04e9578a2307b8c95bb5591c (patch) | |
| tree | ab52096b7ce3007ec7b2744e0f90ce6075b9a844 /opcodes | |
| parent | a62e59897771e2f04fad908fc891714b9bd75d7b (diff) | |
| download | fsf-binutils-gdb-e292aa7a9529771c04e9578a2307b8c95bb5591c.zip fsf-binutils-gdb-e292aa7a9529771c04e9578a2307b8c95bb5591c.tar.gz fsf-binutils-gdb-e292aa7a9529771c04e9578a2307b8c95bb5591c.tar.bz2 | |
Fix disassembly of RX zero-offset register indirect instructions.
opcode * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
opcodes * rx-decode.opc (rx_disp): If the displacement is zero, set the
type to RX_Operand_Zero_Indirect.
* rx-decode.c: Regenerate.
* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
gas * config/rx-parse.y: Allow zero value for 5-bit displacements.
tests * gas/rx/mov.sm: Add tests for zero offset indirect moves.
* gas/rx/mov.d: Update expected output.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/rx-decode.c | 2 | ||||
| -rw-r--r-- | opcodes/rx-decode.opc | 2 | ||||
| -rw-r--r-- | opcodes/rx-dis.c | 10 |
4 files changed, 14 insertions, 7 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8952872..1ca97ee 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2015-11-02 Nick Clifton <nickc@redhat.com> + + * rx-decode.opc (rx_disp): If the displacement is zero, set the + type to RX_Operand_Zero_Indirect. + * rx-decode.c: Regenerate. + * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. + 2015-10-28 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c (aarch64_decode_insn): Add one argument diff --git a/opcodes/rx-decode.c b/opcodes/rx-decode.c index a4e278d..ada3993 100644 --- a/opcodes/rx-decode.c +++ b/opcodes/rx-decode.c @@ -222,7 +222,7 @@ rx_disp (int n, int type, int reg, int size, LocalData * ld) ld->rx->op[n].type = RX_Operand_Register; break; case 0: - ld->rx->op[n].type = RX_Operand_Indirect; + ld->rx->op[n].type = RX_Operand_Zero_Indirect; ld->rx->op[n].addend = 0; break; case 1: diff --git a/opcodes/rx-decode.opc b/opcodes/rx-decode.opc index 7c641fa..2409f7f 100644 --- a/opcodes/rx-decode.opc +++ b/opcodes/rx-decode.opc @@ -221,7 +221,7 @@ rx_disp (int n, int type, int reg, int size, LocalData * ld) ld->rx->op[n].type = RX_Operand_Register; break; case 0: - ld->rx->op[n].type = RX_Operand_Indirect; + ld->rx->op[n].type = RX_Operand_Zero_Indirect; ld->rx->op[n].addend = 0; break; case 1: diff --git a/opcodes/rx-dis.c b/opcodes/rx-dis.c index cab0385..6d4c41a 100644 --- a/opcodes/rx-dis.c +++ b/opcodes/rx-dis.c @@ -168,7 +168,7 @@ print_insn_rx (bfd_vma addr, disassemble_info * dis) oper = opcode.op + *s - '0'; if (do_size) { - if (oper->type == RX_Operand_Indirect) + if (oper->type == RX_Operand_Indirect || oper->type == RX_Operand_Zero_Indirect) PR (PS, "%s", size_names[oper->size]); } else @@ -189,10 +189,10 @@ print_insn_rx (bfd_vma addr, disassemble_info * dis) PR (PS, "%s", register_names[oper->reg]); break; case RX_Operand_Indirect: - if (oper->addend) - PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]); - else - PR (PS, "[%s]", register_names[oper->reg]); + PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]); + break; + case RX_Operand_Zero_Indirect: + PR (PS, "[%s]", register_names[oper->reg]); break; case RX_Operand_Postinc: PR (PS, "[%s+]", register_names[oper->reg]); |