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| author | Robert Suchanek <robert.suchanek@imgtec.com> | 2015-11-09 08:43:09 +0000 |
|---|---|---|
| committer | Robert Suchanek <robert.suchanek@imgtec.com> | 2015-11-09 08:49:10 +0000 |
| commit | be7fe1cddbd5463651e0dff3e8d2cd06455246fc (patch) | |
| tree | 8bb2a34394fbd73a20a6e8cda10bddb2db200ca9 /opcodes | |
| parent | c20a0642333655311b1f5b6f78adfeb8ec9fe1d4 (diff) | |
| download | fsf-binutils-gdb-be7fe1cddbd5463651e0dff3e8d2cd06455246fc.zip fsf-binutils-gdb-be7fe1cddbd5463651e0dff3e8d2cd06455246fc.tar.gz fsf-binutils-gdb-be7fe1cddbd5463651e0dff3e8d2cd06455246fc.tar.bz2 | |
Move copy_u.w to MSA64 ASE, remove copy_u.d.
opcodes/ChangeLog:
* mips-opc.c (mips_builtin_opcodes): Change "copy_u.w" to MSA64 ASE,
remove "copy_u.d".
gas/testsuite/ChangeLog:
* gas/mips/micromips@msa.d: Remove "copy_u.w".
* gas/mips/msa.d: Likewise.
* gas/mips/msa.s: Likweise.
* gas/mips/mipsr6@msa.d: Likewise. Replace addresses with regex.
* gas/mips/msa64.d: Add "copy_u.w". Remove "copy_u.d".
* gas/mips/msa64.s: Likewise.
* gas/mips/micromips@msa64.d: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/mips-opc.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index b29a8ed..402f887 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -3010,8 +3010,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"copy_s.d", "+k,+e+w", 0x78b80019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, {"copy_u.b", "+k,+e+o", 0x78c00019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, {"copy_u.h", "+k,+e+u", 0x78e00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.w", "+k,+e+v", 0x78f00019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.d", "+k,+e+w", 0x78f80019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"copy_u.w", "+k,+e+v", 0x78f00019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 }, {"insert.b", "+d+o,d", 0x79000019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, {"insert.h", "+d+u,d", 0x79200019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, {"insert.w", "+d+v,d", 0x79300019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, |