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authorYufeng Zhang <yufeng.zhang@arm.com>2014-02-27 14:55:46 +0000
committerYufeng Zhang <yufeng.zhang@arm.com>2014-02-27 14:55:46 +0000
commita58549dda5a060d3cadb05dbf54c607a8efb8092 (patch)
tree338ff64b52214ed134099c9bfc8ed72695c42f0e /opcodes
parent2fa0369e5127bff4ea68b596b1984314feb68299 (diff)
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opcodes/
* aarch64-opc.c (print_register_offset_address): Call get_int_reg_name to prepare the register name. gas/testsuite/ * gas/aarch64/ldst-reg-reg-offset.s: Add tests. * gas/aarch64/ldst-reg-reg-offset.d: Update.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/aarch64-opc.c7
2 files changed, 10 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ac1d8fb..b7bfe64 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64-opc.c (print_register_offset_address): Call
+ get_int_reg_name to prepare the register name.
+
2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
* i386-opc.tbl: Remove wrong variant of vcvtps2ph
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4313327..a84c758 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2282,9 +2282,12 @@ print_register_offset_address (char *buf, size_t size,
else
tb[0] = '\0';
- snprintf (buf, size, "[%s,%c%d%s]",
+ snprintf (buf, size, "[%s,%s%s]",
get_64bit_int_reg_name (opnd->addr.base_regno, 1),
- wm_p ? 'w' : 'x', opnd->addr.offset.regno, tb);
+ get_int_reg_name (opnd->addr.offset.regno,
+ wm_p ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X,
+ 0 /* sp_reg_p */),
+ tb);
}
/* Generate the string representation of the operand OPNDS[IDX] for OPCODE