Add -Wshadow to the gcc command line options used when compiling the binutils.

Fix up all warnings generated by the addition of this switch.

29 files changed, 332 insertions, 313 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9e2dfbd..04d35ff 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,34 @@
+2009-12-11  Nick Clifton  <nickc@redhat.com>
+
+	* Makefile.in: Regenerate.
+	* configure: Regenerate.
+	* arm-dis.c: Fix shadowed variable warnings.
+	* cgen-opc.c: Likewise.
+	* cr16-dis.c: Likewise.
+	* crx-dis.c: Likewise.
+	* d30v-dis.c: Likewise.
+	* fr30-dis.c: Likewise.
+	* frv-opc.c: Likewise.
+	* h8500-dis.c: Likewise.
+	* i386-dis.c: Likewise.
+	* i960-dis.c: Likewise.
+	* ia64-gen.c: Likewise.
+	* ia64-opc.c: Likewise.
+	* m32c-asm.c: Likewise.
+	* m32c-dis.c: Likewise.
+	* m68k-dis.c: Likewise.
+	* maxq-dis.c: Likewise.
+	* mcore-dis.c: Likewise.
+	* mep-asm.c: Likewise.
+	* microblaze-dis.c: Likewise.
+	* mmix-dis.c: Likewise.
+	* ns32k-dis.c: Likewise.
+	* or32-opc.c: Likewise.
+	* s390-dis.c: Likewise.
+	* sh64-dis.c: Likewise.
+	* spu-dis.c: Likewise.
+	* tic30-dis.c: Likewise.
+
 2009-12-09  Nick Clifton  <nickc@redhat.com>
 
 	PR 10924
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 4b9c47d..6b6aae8 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -45,6 +45,7 @@ DIST_COMMON = ChangeLog $(srcdir)/Makefile.in $(srcdir)/Makefile.am \
 	$(top_srcdir)/po/Make-in $(srcdir)/../depcomp
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
+	$(top_srcdir)/../config/zlib.m4 \
 	$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
 	$(top_srcdir)/../config/depstand.m4 \
 	$(top_srcdir)/../config/gettext-sister.m4 \
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 3bfad52..88b5cf1 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1973,7 +1973,6 @@ print_insn_coprocessor (bfd_vma pc,
 		case '5': case '6': case '7': case '8': case '9':
 		  {
 		    int width;
-		    unsigned long value;
 
 		    c = arm_decode_bitfield (c, given, &value, &width);
 
@@ -2142,7 +2141,6 @@ print_insn_coprocessor (bfd_vma pc,
 
 		  case 'Z':
 		    {
-		      int value;
 		      /* given (20, 23) | given (0, 3) */
 		      value = ((given >> 16) & 0xf0) | (given & 0xf);
 		      func (stream, "%d", value);
@@ -2537,7 +2535,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
 			func (stream, "}, [%s", arm_regnames[rn]);
 			if (align)
 			  {
-                            int align = (8 * (type + 1)) << size;
+                            align = (8 * (type + 1)) << size;
                             if (type == 3)
                               align = (size > 1) ? align >> 1 : align;
 			    if (type == 2 || (type == 0 && !size))
@@ -3171,10 +3169,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			{
 			  long msb = (given & 0x001f0000) >> 16;
 			  long lsb = (given & 0x00000f80) >> 7;
-			  long width = msb - lsb + 1;
+			  long w = msb - lsb + 1;
 
-			  if (width > 0)
-			    func (stream, "#%lu, #%lu", lsb, width);
+			  if (w > 0)
+			    func (stream, "#%lu, #%lu", lsb, w);
 			  else
 			    func (stream, "(invalid: %lu:%lu)", lsb, msb);
 			}
diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c
index 7d52284..263eb2c 100644
--- a/opcodes/cgen-opc.c
+++ b/opcodes/cgen-opc.c
@@ -376,10 +376,11 @@ cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length)
 
       for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */
 	{
-	  int index;
+	  int bit_index;
 	  bfd_vma this_value;
-	  index = i; /* NB: not dependent on endianness; opposite of cgen_put_insn_value! */
-	  this_value = bfd_get_bits (& buf[index / 8], insn_chunk_bitsize, big_p);
+
+	  bit_index = i; /* NB: not dependent on endianness; opposite of cgen_put_insn_value! */
+	  this_value = bfd_get_bits (& buf[bit_index / 8], insn_chunk_bitsize, big_p);
 	  value = (value << insn_chunk_bitsize) | this_value;
 	}
     }
@@ -414,9 +415,10 @@ cgen_put_insn_value (CGEN_CPU_DESC cd,
 
       for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */
 	{
-	  int index;
-	  index = (length - insn_chunk_bitsize - i); /* NB: not dependent on endianness! */
-	  bfd_put_bits ((bfd_vma) value, & buf[index / 8], insn_chunk_bitsize, big_p);
+	  int bit_index;
+
+	  bit_index = (length - insn_chunk_bitsize - i); /* NB: not dependent on endianness! */
+	  bfd_put_bits ((bfd_vma) value, & buf[bit_index / 8], insn_chunk_bitsize, big_p);
 	  value >>= insn_chunk_bitsize;
 	}
     }
diff --git a/opcodes/configure b/opcodes/configure
index 83b973c..67fab59 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -11376,7 +11376,7 @@ esac
 fi
 
 
-GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes"
+GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow"
 
 # Check whether --enable-werror was given.
 if test "${enable_werror+set}" = set; then :
diff --git a/opcodes/cr16-dis.c b/opcodes/cr16-dis.c
index 3a31d92..0aaf61c 100644
--- a/opcodes/cr16-dis.c
+++ b/opcodes/cr16-dis.c
@@ -162,9 +162,9 @@ getargtype (operand_type op)
    string. This routine is used when disassembling the 'CC' instruction.  */
 
 static char *
-getccstring (unsigned cc)
+getccstring (unsigned cc_insn)
 {
-  return (char *) cr16_b_cond_tab[cc];
+  return (char *) cr16_b_cond_tab[cc_insn];
 }
 
 
@@ -187,12 +187,12 @@ getcinvstring (const char *str)
    This routine is used when disassembling the 'excp' instruction.  */
 
 static char *
-gettrapstring (unsigned int index)
+gettrapstring (unsigned int trap_index)
 {
   const trap_entry *trap;
 
   for (trap = cr16_traps; trap < cr16_traps + NUMTRAPS; trap++)
-    if (trap->entry == index)
+    if (trap->entry == trap_index)
       return trap->name;
 
   return ILLEGAL;
@@ -203,12 +203,12 @@ gettrapstring (unsigned int index)
 static char *
 getregname (reg r)
 {
-  const reg_entry *reg = cr16_regtab + r;
+  const reg_entry * regentry = cr16_regtab + r;
 
-  if (reg->type != CR16_R_REGTYPE)
+  if (regentry->type != CR16_R_REGTYPE)
     return ILLEGAL;
 
-  return reg->name;
+  return regentry->name;
 }
 
 /* Given a register pair enum value, retrieve its name.  */
@@ -216,12 +216,12 @@ getregname (reg r)
 static char *
 getregpname (reg r)
 {
-  const reg_entry *reg = cr16_regptab + r;
+  const reg_entry * regentry = cr16_regptab + r;
 
-  if (reg->type != CR16_RP_REGTYPE)
+  if (regentry->type != CR16_RP_REGTYPE)
     return ILLEGAL;
 
-  return reg->name;
+  return regentry->name;
 }
 
 /* Given a index register pair enum value, retrieve its name.  */
@@ -229,7 +229,7 @@ getregpname (reg r)
 static char *
 getidxregpname (reg r)
 {
-  const reg_entry *reg;
+  const reg_entry * regentry;
 
   switch (r)
    {
@@ -245,23 +245,23 @@ getidxregpname (reg r)
      break;
    }
 
-  reg = cr16_regptab + r;
+  regentry = cr16_regptab + r;
 
-  if (reg->type != CR16_RP_REGTYPE)
+  if (regentry->type != CR16_RP_REGTYPE)
     return ILLEGAL;
 
-  return reg->name;
+  return regentry->name;
 }
 
 /* Getting a processor register name.  */
 
 static char *
-getprocregname (int index)
+getprocregname (int reg_index)
 {
   const reg_entry *r;
 
   for (r = cr16_pregtab; r < cr16_pregtab + NUMPREGS; r++)
-    if (r->image == index)
+    if (r->image == reg_index)
       return r->name;
 
   return "ILLEGAL REGISTER";
@@ -270,12 +270,12 @@ getprocregname (int index)
 /* Getting a processor register name - 32 bit size.  */
 
 static char *
-getprocpregname (int index)
+getprocpregname (int reg_index)
 {
   const reg_entry *r;
 
   for (r = cr16_pregptab; r < cr16_pregptab + NUMPREGPS; r++)
-    if (r->image == index)
+    if (r->image == reg_index)
       return r->name;
 
   return "ILLEGAL REGISTER";
@@ -697,7 +697,7 @@ print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info)
 /* Print all the arguments of CURRINSN instruction.  */
 
 static void
-print_arguments (ins *currInsn, bfd_vma memaddr, struct disassemble_info *info)
+print_arguments (ins *currentInsn, bfd_vma memaddr, struct disassemble_info *info)
 {
   int i;
 
@@ -705,13 +705,13 @@ print_arguments (ins *currInsn, bfd_vma memaddr, struct disassemble_info *info)
   if ((IS_INSN_MNEMONIC ("pop")
        || (IS_INSN_MNEMONIC ("popret")
 	   || (IS_INSN_MNEMONIC ("push"))))
-      && currInsn->nargs == 1)
+      && currentInsn->nargs == 1)
     {
       info->fprintf_func (info->stream, "RA");
       return;
     }
 
-  for (i = 0; i < currInsn->nargs; i++)
+  for (i = 0; i < currentInsn->nargs; i++)
     {
       processing_argument_number = i;
 
@@ -725,9 +725,9 @@ print_arguments (ins *currInsn, bfd_vma memaddr, struct disassemble_info *info)
       if ((INST_HAS_REG_LIST) && (i == 2))
         info->fprintf_func (info->stream, "RA");
       else
-        print_arg (&currInsn->arg[i], memaddr, info);
+        print_arg (&currentInsn->arg[i], memaddr, info);
 
-      if ((i != currInsn->nargs - 1) && (!IS_INSN_MNEMONIC ("b")))
+      if ((i != currentInsn->nargs - 1) && (!IS_INSN_MNEMONIC ("b")))
         info->fprintf_func (info->stream, ",");
     }
 }
diff --git a/opcodes/crx-dis.c b/opcodes/crx-dis.c
index c752457..f909897 100644
--- a/opcodes/crx-dis.c
+++ b/opcodes/crx-dis.c
@@ -155,12 +155,12 @@ getargtype (operand_type op)
    This routine is used when disassembling the 'excp' instruction.  */
 
 static char *
-gettrapstring (unsigned int index)
+gettrapstring (unsigned int trap_index)
 {
   const trap_entry *trap;
 
   for (trap = crx_traps; trap < crx_traps + NUMTRAPS; trap++)
-    if (trap->entry == index)
+    if (trap->entry == trap_index)
       return trap->name;
 
   return ILLEGAL;
@@ -186,12 +186,12 @@ getcinvstring (unsigned int num)
 char *
 getregname (reg r)
 {
-  const reg_entry *reg = &crx_regtab[r];
+  const reg_entry * regentry = &crx_regtab[r];
 
-  if (reg->type != CRX_R_REGTYPE)
+  if (regentry->type != CRX_R_REGTYPE)
     return ILLEGAL;
   else
-    return reg->name;
+    return regentry->name;
 }
 
 /* Given a coprocessor register enum value, retrieve its name.  */
@@ -199,28 +199,28 @@ getregname (reg r)
 char *
 getcopregname (copreg r, reg_type type)
 {
-  const reg_entry *reg;
+  const reg_entry * regentry;
 
   if (type == CRX_C_REGTYPE)
-    reg = &crx_copregtab[r];
+    regentry = &crx_copregtab[r];
   else if (type == CRX_CS_REGTYPE)
-    reg = &crx_copregtab[r+(cs0-c0)];
+    regentry = &crx_copregtab[r+(cs0-c0)];
   else
     return ILLEGAL;
 
-  return reg->name;
+  return regentry->name;
 }
 
 
 /* Getting a processor register name.  */
 
 static char *
-getprocregname (int index)
+getprocregname (int reg_index)
 {
   const reg_entry *r;
 
   for (r = crx_regtab; r < crx_regtab + NUMREGS; r++)
-    if (r->image == index)
+    if (r->image == reg_index)
       return r->name;
 
   return "ILLEGAL REGISTER";
@@ -634,17 +634,17 @@ print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info)
 /* Print all the arguments of CURRINSN instruction.  */
 
 static void
-print_arguments (ins *currInsn, bfd_vma memaddr, struct disassemble_info *info)
+print_arguments (ins *currentInsn, bfd_vma memaddr, struct disassemble_info *info)
 {
   int i;
 
-  for (i = 0; i < currInsn->nargs; i++)
+  for (i = 0; i < currentInsn->nargs; i++)
     {
       processing_argument_number = i;
 
-      print_arg (&currInsn->arg[i], memaddr, info);
+      print_arg (&currentInsn->arg[i], memaddr, info);
 
-      if (i != currInsn->nargs - 1)
+      if (i != currentInsn->nargs - 1)
 	info->fprintf_func (info->stream, ", ");
     }
 }
diff --git a/opcodes/d30v-dis.c b/opcodes/d30v-dis.c
index ec21305..5f5d07f 100644
--- a/opcodes/d30v-dis.c
+++ b/opcodes/d30v-dis.c
@@ -34,7 +34,7 @@
 static int
 lookup_opcode (struct d30v_insn *insn, long num, int is_long)
 {
-  int i = 0, index;
+  int i = 0, op_index;
   struct d30v_format *f;
   struct d30v_opcode *op = (struct d30v_opcode *) d30v_opcode_table;
   int op1 = (num >> 25) & 0x7;
@@ -56,11 +56,11 @@ lookup_opcode (struct d30v_insn *insn, long num, int is_long)
   while (op->op1 == op1 && op->op2 == op2)
     {
       /* Scan through all the formats for the opcode.  */
-      index = op->format[i++];
+      op_index = op->format[i++];
       do
 	{
-	  f = (struct d30v_format *) &d30v_format_table[index];
-	  while (f->form == index)
+	  f = (struct d30v_format *) &d30v_format_table[op_index];
+	  while (f->form == op_index)
 	    {
 	      if ((!is_long || f->form >= LONG) && (f->modifier == mod))
 		{
@@ -72,7 +72,7 @@ lookup_opcode (struct d30v_insn *insn, long num, int is_long)
 	  if (insn->form)
 	    break;
 	}
-      while ((index = op->format[i++]) != 0);
+      while ((op_index = op->format[i++]) != 0);
       if (insn->form)
 	break;
       op++;
diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index 6f82bd7..807a5fd 100644
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -67,7 +67,7 @@ print_register_list (void * dis_info,
 {
   disassemble_info *info = dis_info;
   int mask;
-  int index = 0;
+  int reg_index = 0;
   char * comma = "";
 
   if (load_store)
@@ -77,11 +77,11 @@ print_register_list (void * dis_info,
 
   if (value & mask)
     {
-      (*info->fprintf_func) (info->stream, "r%li", index + offset);
+      (*info->fprintf_func) (info->stream, "r%li", reg_index + offset);
       comma = ",";
     }
     
-  for (index = 1; index <= 7; ++index)
+  for (reg_index = 1; reg_index <= 7; ++reg_index)
     {
       if (load_store)
 	mask >>= 1;
@@ -90,7 +90,7 @@ print_register_list (void * dis_info,
 
       if (value & mask)
 	{
-	  (*info->fprintf_func) (info->stream, "%sr%li", comma, index + offset);
+	  (*info->fprintf_func) (info->stream, "%sr%li", comma, reg_index + offset);
 	  comma = ",";
 	}
     }
diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c
index 8da1596..3abe96e 100644
--- a/opcodes/frv-opc.c
+++ b/opcodes/frv-opc.c
@@ -795,7 +795,7 @@ check_insn_major_constraints (FRV_VLIW *vliw,
 int
 frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
 {
-  int index;
+  int slot_index;
   CGEN_ATTR_VALUE_ENUM_TYPE major;
   CGEN_ATTR_VALUE_ENUM_TYPE unit;
   VLIW_COMBO *new_vliw;
@@ -803,8 +803,8 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
   if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn))
     return 1;
 
-  index = vliw->next_slot;
-  if (index >= FRV_VLIW_SIZE)
+  slot_index = vliw->next_slot;
+  if (slot_index >= FRV_VLIW_SIZE)
     return 1;
 
   unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT);
@@ -831,7 +831,7 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
       break;
     }
 
-  if (index <= 0)
+  if (slot_index <= 0)
     {
       /* Any insn can be added to slot 0.  */
       while (! match_unit (vliw, unit, (*vliw->current_vliw)[0]))
@@ -851,8 +851,8 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
       if (new_vliw && check_insn_major_constraints (vliw, major, insn))
 	{
 	  vliw->current_vliw = new_vliw;
-	  vliw->major[index] = major;
-	  vliw->insn[index] = insn;
+	  vliw->major[slot_index] = major;
+	  vliw->insn[slot_index] = insn;
 	  vliw->next_slot++;
 	  return 0;
 	}
diff --git a/opcodes/h8500-dis.c b/opcodes/h8500-dis.c
index d19ef7f..1c9463a 100644
--- a/opcodes/h8500-dis.c
+++ b/opcodes/h8500-dis.c
@@ -97,7 +97,7 @@ print_insn_h8500 (bfd_vma addr, disassemble_info *info)
       int rd = 0;
       int rs = 0;
       int disp = 0;
-      int abs = 0;
+      int abs_val = 0;
       int imm = 0;
       int pcrel = 0;
       int qim = 0;
@@ -154,17 +154,17 @@ print_insn_h8500 (bfd_vma addr, disassemble_info *info)
 		  break;
 		case ABS24:
 		  FETCH_DATA (info, buffer + byte + 3);
-		  abs =
+		  abs_val =
 		    (buffer[byte] << 16)
 		    | (buffer[byte + 1] << 8)
 		    | (buffer[byte + 2]);
 		  break;
 		case ABS16:
 		  FETCH_DATA (info, buffer + byte + 2);
-		  abs = (buffer[byte] << 8) | (buffer[byte + 1]);
+		  abs_val = (buffer[byte] << 8) | (buffer[byte + 1]);
 		  break;
 		case ABS8:
-		  abs = (buffer[byte]);
+		  abs_val = (buffer[byte]);
 		  break;
 		case IMM16:
 		  FETCH_DATA (info, buffer + byte + 2);
@@ -265,28 +265,28 @@ print_insn_h8500 (bfd_vma addr, disassemble_info *info)
 	      func (stream, "@-sp");
 	      break;
 	    case ABS24:
-	      func (stream, "@0x%0x:24", abs);
+	      func (stream, "@0x%0x:24", abs_val);
 	      break;
 	    case ABS16:
-	      func (stream, "@0x%0x:16", abs & 0xffff);
+	      func (stream, "@0x%0x:16", abs_val & 0xffff);
 	      break;
 	    case ABS8:
-	      func (stream, "@0x%0x:8", abs & 0xff);
+	      func (stream, "@0x%0x:8", abs_val & 0xff);
 	      break;
 	    case IMM16:
 	      func (stream, "#0x%0x:16", imm & 0xffff);
 	      break;
 	    case RLIST:
 	      {
-		int i;
+		int j;
 		int nc = 0;
 
 		func (stream, "(");
-		for (i = 0; i < 8; i++)
+		for (j = 0; j < 8; j++)
 		  {
-		    if (imm & (1 << i))
+		    if (imm & (1 << j))
 		      {
-			func (stream, "r%d", i);
+			func (stream, "r%d", j);
 			if (nc)
 			  func (stream, ",");
 			nc = 1;
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 0e5b0ab..5ecf963 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -10204,7 +10204,7 @@ with the -M switch (multiple options should be separated by commas):\n"));
 static const struct dis386 *
 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
 {
-  int index, vex_table_index;
+  int vindex, vex_table_index;
 
   if (dp->name != NULL)
     return dp;
@@ -10216,8 +10216,8 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       break;
 
     case USE_MOD_TABLE:
-      index = modrm.mod == 0x3 ? 1 : 0;
-      dp = &mod_table[dp->op[1].bytemode][index];
+      vindex = modrm.mod == 0x3 ? 1 : 0;
+      dp = &mod_table[dp->op[1].bytemode][vindex];
       break;
 
     case USE_RM_TABLE:
@@ -10231,16 +10231,16 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
 	  switch (vex.prefix)
 	    {
 	    case 0:
-	      index = 0;
+	      vindex = 0;
 	      break;
 	    case REPE_PREFIX_OPCODE:
-	      index = 1;
+	      vindex = 1;
 	      break;
 	    case DATA_PREFIX_OPCODE:
-	      index = 2;
+	      vindex = 2;
 	      break;
 	    case REPNE_PREFIX_OPCODE:
-	      index = 3;
+	      vindex = 3;
 	      break;
 	    default:
 	      abort ();
@@ -10249,11 +10249,11 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
 	}
       else 
 	{
-	  index = 0;
+	  vindex = 0;
 	  used_prefixes |= (prefixes & PREFIX_REPZ);
 	  if (prefixes & PREFIX_REPZ)
 	    {
-	      index = 1;
+	      vindex = 1;
 	      all_prefixes[last_repz_prefix] = 0;
 	    }
 	  else
@@ -10263,7 +10263,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
 	      used_prefixes |= (prefixes & PREFIX_REPNZ);
 	      if (prefixes & PREFIX_REPNZ)
 		{
-		  index = 3;
+		  vindex = 3;
 		  all_prefixes[last_repnz_prefix] = 0;
 		}
 	      else
@@ -10271,24 +10271,24 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
 		  used_prefixes |= (prefixes & PREFIX_DATA);
 		  if (prefixes & PREFIX_DATA)
 		    {
-		      index = 2;
+		      vindex = 2;
 		      all_prefixes[last_data_prefix] = 0;
 		    }
 		}
 	    }
 	}
-      dp = &prefix_table[dp->op[1].bytemode][index];
+      dp = &prefix_table[dp->op[1].bytemode][vindex];
       break;
 
     case USE_X86_64_TABLE:
-      index = address_mode == mode_64bit ? 1 : 0;
-      dp = &x86_64_table[dp->op[1].bytemode][index];
+      vindex = address_mode == mode_64bit ? 1 : 0;
+      dp = &x86_64_table[dp->op[1].bytemode][vindex];
       break;
 
     case USE_3BYTE_TABLE:
       FETCH_DATA (info, codep + 2);
-      index = *codep++;
-      dp = &three_byte_table[dp->op[1].bytemode][index];
+      vindex = *codep++;
+      dp = &three_byte_table[dp->op[1].bytemode][vindex];
       modrm.mod = (*codep >> 6) & 3;
       modrm.reg = (*codep >> 3) & 7;
       modrm.rm = *codep & 7;
@@ -10301,17 +10301,17 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       switch (vex.length)
 	{
 	case 128:
-	  index = 0;
+	  vindex = 0;
 	  break;
 	case 256:
-	  index = 1;
+	  vindex = 1;
 	  break;
 	default:
 	  abort ();
 	  break;
 	}
 
-      dp = &vex_len_table[dp->op[1].bytemode][index];
+      dp = &vex_len_table[dp->op[1].bytemode][vindex];
       break;
 
     case USE_XOP_8F_TABLE:
@@ -10364,8 +10364,8 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       need_vex = 1;
       need_vex_reg = 1;
       codep++;
-      index = *codep++;
-      dp = &xop_table[vex_table_index][index];
+      vindex = *codep++;
+      dp = &xop_table[vex_table_index][vindex];
 
       FETCH_DATA (info, codep + 1);
       modrm.mod = (*codep >> 6) & 3;
@@ -10421,10 +10421,10 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       need_vex = 1;
       need_vex_reg = 1;
       codep++;
-      index = *codep++;
-      dp = &vex_table[vex_table_index][index];
+      vindex = *codep++;
+      dp = &vex_table[vex_table_index][vindex];
       /* There is no MODRM byte for VEX [82|77].  */
-      if (index != 0x77 && index != 0x82)
+      if (vindex != 0x77 && vindex != 0x82)
 	{
 	  FETCH_DATA (info, codep + 1);
 	  modrm.mod = (*codep >> 6) & 3;
@@ -10463,10 +10463,10 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
       need_vex = 1;
       need_vex_reg = 1;
       codep++;
-      index = *codep++;
-      dp = &vex_table[dp->op[1].bytemode][index];
+      vindex = *codep++;
+      dp = &vex_table[dp->op[1].bytemode][vindex];
       /* There is no MODRM byte for VEX [82|77].  */
-      if (index != 0x77 && index != 0x82)
+      if (vindex != 0x77 && vindex != 0x82)
 	{
 	  FETCH_DATA (info, codep + 1);
 	  modrm.mod = (*codep >> 6) & 3;
@@ -12158,7 +12158,7 @@ OP_E_memory (int bytemode, int sizeflag)
       int haveindex;
       int needindex;
       int base, rbase;
-      int index = 0;
+      int vindex = 0;
       int scale = 0;
 
       havesib = 0;
@@ -12170,13 +12170,13 @@ OP_E_memory (int bytemode, int sizeflag)
 	{
 	  havesib = 1;
 	  FETCH_DATA (the_info, codep + 1);
-	  index = (*codep >> 3) & 7;
+	  vindex = (*codep >> 3) & 7;
 	  scale = (*codep >> 6) & 3;
 	  base = *codep & 7;
 	  USED_REX (REX_X);
 	  if (rex & REX_X)
-	    index += 8;
-	  haveindex = index != 4;
+	    vindex += 8;
+	  haveindex = vindex != 4;
 	  codep++;
 	}
       rbase = base + add;
@@ -12260,7 +12260,7 @@ OP_E_memory (int bytemode, int sizeflag)
 		  if (haveindex)
 		    oappend (address_mode == mode_64bit 
 			     && (sizeflag & AFLAG)
-			     ? names64[index] : names32[index]);
+			     ? names64[vindex] : names32[vindex]);
 		  else
 		    oappend (address_mode == mode_64bit 
 			     && (sizeflag & AFLAG)
diff --git a/opcodes/i960-dis.c b/opcodes/i960-dis.c
index 52eb86e..53d723c 100644
--- a/opcodes/i960-dis.c
+++ b/opcodes/i960-dis.c
@@ -824,7 +824,7 @@ ea (bfd_vma memaddr, int mode, const char *reg2, const char *reg3, int word1,
 /* Register Instruction Operand.  */
 
 static void
-regop (int mode, int spec, int reg, int fp)
+regop (int mode, int spec, int fp_reg, int fp)
 {
   if (fp)
     {
@@ -832,7 +832,7 @@ regop (int mode, int spec, int reg, int fp)
       if (mode == 1)
 	{
 	  /* FP operand.  */
-	  switch (reg)
+	  switch (fp_reg)
 	    {
 	    case 0:  (*info->fprintf_func) (stream, "fp0");
 	      break;
@@ -853,7 +853,7 @@ regop (int mode, int spec, int reg, int fp)
       else
 	{
 	  /* Non-FP register.  */
-	  (*info->fprintf_func) (stream, reg_names[reg]);
+	  (*info->fprintf_func) (stream, reg_names[fp_reg]);
 	}
     }
   else
@@ -862,15 +862,15 @@ regop (int mode, int spec, int reg, int fp)
       if (mode == 1)
 	{
 	  /* Literal.  */
-	  (*info->fprintf_func) (stream, "%d", reg);
+	  (*info->fprintf_func) (stream, "%d", fp_reg);
 	}
       else
 	{
 	  /* Register.  */
 	  if (spec == 0)
-	    (*info->fprintf_func) (stream, reg_names[reg]);
+	    (*info->fprintf_func) (stream, reg_names[fp_reg]);
 	  else
-	    (*info->fprintf_func) (stream, "sf%d", reg);
+	    (*info->fprintf_func) (stream, "sf%d", fp_reg);
 	}
     }
 }
@@ -878,15 +878,15 @@ regop (int mode, int spec, int reg, int fp)
 /* Register Instruction Destination Operand.  */
 
 static void
-dstop (int mode, int reg, int fp)
+dstop (int mode, int dest_reg, int fp)
 {
   /* 'dst' operand can't be a literal. On non-FP instructions,  register
      mode is assumed and "m3" acts as if were "s3";  on FP-instructions,
      sf registers are not allowed so m3 acts normally.  */
   if (fp)
-    regop (mode, 0, reg, fp);
+    regop (mode, 0, dest_reg, fp);
   else
-    regop (0, mode, reg, fp);
+    regop (0, mode, dest_reg, fp);
 }
 
 static void
diff --git a/opcodes/ia64-gen.c b/opcodes/ia64-gen.c
index 587fd8a..eefa81c 100644
--- a/opcodes/ia64-gen.c
+++ b/opcodes/ia64-gen.c
@@ -2697,7 +2697,7 @@ static void
 print_main_table (void)
 {
   struct main_entry *ptr = maintable;
-  int index = 0;
+  int tindex = 0;
 
   printf ("static const struct ia64_main_table\nmain_table[] = {\n");
   while (ptr != NULL)
@@ -2718,7 +2718,7 @@ print_main_table (void)
 	      ptr->opcode->flags,
 	      ptr->completers->num);
 
-      ptr->main_index = index++;
+      ptr->main_index = tindex++;
 
       ptr = ptr->next;
     }
diff --git a/opcodes/ia64-opc.c b/opcodes/ia64-opc.c
index 7938fbc..539fa9b 100644
--- a/opcodes/ia64-opc.c
+++ b/opcodes/ia64-opc.c
@@ -1,5 +1,5 @@
 /* ia64-opc.c -- Functions to access the compacted opcode table
-   Copyright 1999, 2000, 2001, 2003, 2005, 2007 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2003, 2005, 2007, 2009 Free Software Foundation, Inc.
    Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com>
 
    This file is part of the GNU opcodes library.
@@ -718,13 +718,13 @@ ia64_free_opcode (struct ia64_opcode *ent)
 }
 
 const struct ia64_dependency *
-ia64_find_dependency (int index)
+ia64_find_dependency (int dep_index)
 {
-  index = DEP(index);
+  dep_index = DEP(dep_index);
 
-  if (index < 0
-      || index >= (int)(sizeof(dependencies) / sizeof(dependencies[0])))
+  if (dep_index < 0
+      || dep_index >= (int) ARRAY_SIZE (dependencies))
     return NULL;
 
-  return &dependencies[index];
+  return &dependencies[dep_index];
 }
diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c
index c45d91d..d5168b2 100644
--- a/opcodes/m32c-asm.c
+++ b/opcodes/m32c-asm.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-asm.in isn't
 
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2009
    Free Software Foundation, Inc.
 
    This file is part of libopcodes.
@@ -125,27 +125,26 @@ parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp,
 		 int opindex, unsigned long *valuep)
 {
   const char *errmsg = 0;
-  unsigned long value;
+  unsigned long value = 0;
   long have_zero = 0;
 
   if (strncasecmp (*strp, "%dsp8(", 6) == 0)
     {
       enum cgen_parse_operand_result result_type;
-      bfd_vma value;
-      const char *errmsg;
+      bfd_vma val;
 
       *strp += 6;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_8,
-				   & result_type, & value);
+				   & result_type, & val);
       if (**strp != ')')
 	return _("missing `)'");
       (*strp) ++;
 
       if (errmsg == NULL
   	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	{
-	  return _("%dsp8() takes a symbolic address, not a number");
-	}
+	return _("%dsp8() takes a symbolic address, not a number");
+
+      value = val;
       *valuep = value;
       return errmsg;
     }
@@ -222,26 +221,25 @@ parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
 	       int opindex, signed long *valuep)
 {
   const char *errmsg = 0;
-  signed long value;
+  signed long value = 0;
 
   if (strncasecmp (*strp, "%hi8(", 5) == 0)
     {
       enum cgen_parse_operand_result result_type;
-      bfd_vma value;
-      const char *errmsg;
+      bfd_vma val;
 
       *strp += 5;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32C_HI8,
-				   & result_type, & value);
+				   & result_type, & val);
       if (**strp != ')')
 	return _("missing `)'");
       (*strp) ++;
 
       if (errmsg == NULL
   	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	{
-	  value >>= 16;
-	}
+	val >>= 16;
+
+      value = val;
       *valuep = value;
       return errmsg;
     }
@@ -263,27 +261,26 @@ parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp,
 		 int opindex, unsigned long *valuep)
 {
   const char *errmsg = 0;
-  unsigned long value;
+  unsigned long value = 0;
   long have_zero = 0;
 
   if (strncasecmp (*strp, "%dsp16(", 7) == 0)
     {
       enum cgen_parse_operand_result result_type;
-      bfd_vma value;
-      const char *errmsg;
+      bfd_vma val;
 
       *strp += 7;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
-				   & result_type, & value);
+				   & result_type, & val);
       if (**strp != ')')
 	return _("missing `)'");
       (*strp) ++;
 
       if (errmsg == NULL
   	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	{
-	  return _("%dsp16() takes a symbolic address, not a number");
-	}
+	return _("%dsp16() takes a symbolic address, not a number");
+
+      value = val;
       *valuep = value;
       return errmsg;
     }
@@ -323,26 +320,25 @@ parse_signed16 (CGEN_CPU_DESC cd, const char **strp,
 	       int opindex, signed long *valuep)
 {
   const char *errmsg = 0;
-  signed long value;
+  signed long value = 0;
 
   if (strncasecmp (*strp, "%lo16(", 6) == 0)
     {
       enum cgen_parse_operand_result result_type;
-      bfd_vma value;
-      const char *errmsg;
+      bfd_vma val;
 
       *strp += 6;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
-				   & result_type, & value);
+				   & result_type, & val);
       if (**strp != ')')
 	return _("missing `)'");
       (*strp) ++;
 
       if (errmsg == NULL
   	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	{
-	  value &= 0xffff;
-	}
+	val &= 0xffff;
+
+      value = val;
       *valuep = value;
       return errmsg;
     }
@@ -350,21 +346,20 @@ parse_signed16 (CGEN_CPU_DESC cd, const char **strp,
   if (strncasecmp (*strp, "%hi16(", 6) == 0)
     {
       enum cgen_parse_operand_result result_type;
-      bfd_vma value;
-      const char *errmsg;
+      bfd_vma val;
 
       *strp += 6;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
-				   & result_type, & value);
+				   & result_type, & val);
       if (**strp != ')')
 	return _("missing `)'");
       (*strp) ++;
 
       if (errmsg == NULL
   	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	{
-	  value >>= 16;
-	}
+	val >>= 16;
+
+      value = val;
       *valuep = value;
       return errmsg;
     }
diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c
index 1b912d9..e78bcd1 100644
--- a/opcodes/m32c-dis.c
+++ b/opcodes/m32c-dis.c
@@ -210,7 +210,7 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
   };
   disassemble_info *info = dis_info;
   int mask;
-  int index = 0;
+  int reg_index = 0;
   char* comma = "";
 
   if (push)
@@ -224,7 +224,7 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       comma = ",";
     }
 
-  for (index = 1; index <= 7; ++index)
+  for (reg_index = 1; reg_index <= 7; ++reg_index)
     {
       if (push)
         mask >>= 1;
@@ -234,7 +234,7 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       if (value & mask)
         {
           (*info->fprintf_func) (info->stream, "%s%s", comma,
-				 m16c_register_names [index]);
+				 m16c_register_names [reg_index]);
           comma = ",";
         }
     }
diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c
index 627abcc..326e429 100644
--- a/opcodes/m68k-dis.c
+++ b/opcodes/m68k-dis.c
@@ -1232,7 +1232,6 @@ print_insn_arg (const char *d,
     case '2':
     case '3':
       {
-	int val;
 	char *name = 0;
 
 	FETCH_ARG (5, val);
diff --git a/opcodes/maxq-dis.c b/opcodes/maxq-dis.c
index d9977ea..2f82c4d 100644
--- a/opcodes/maxq-dis.c
+++ b/opcodes/maxq-dis.c
@@ -1,6 +1,6 @@
 /* Instruction printing code for the MAXQ
 
-   Copyright 2004, 2005, 2007 Free Software Foundation, Inc.
+   Copyright 2004, 2005, 2007, 2009 Free Software Foundation, Inc.
 
    Written by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
    S.(inderpreetb@noida.hcltech.com)
@@ -151,21 +151,21 @@ static char *
 get_reg_name (unsigned char reg_code, type1 arg_pos)
 {
   unsigned char module;
-  unsigned char index;
+  unsigned char r_index;
   int ix = 0;
   reg_entry const *reg_x;
   mem_access_syntax const *syntax;
   mem_access *mem_acc;
 
   module = 0;
-  index = 0;
+  r_index = 0;
   module = (reg_code & MASK_LOW_BYTE);
-  index = (reg_code & MASK_HIGH_BYTE);
-  index = index >> 4;
+  r_index = (reg_code & MASK_HIGH_BYTE);
+  r_index = r_index >> 4;
 
   /* Search the system register table.  */
   for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL; ++reg_x)
-    if ((reg_x->Mod_name == module) && (reg_x->Mod_index == index))
+    if ((reg_x->Mod_name == module) && (reg_x->Mod_index == r_index))
       return reg_x->reg_name;
 
   /* Serch pheripheral table.  */
@@ -173,7 +173,7 @@ get_reg_name (unsigned char reg_code, type1 arg_pos)
     {
       reg_x = &new_reg_table[ix];
 
-      if ((reg_x->Mod_name == module) && (reg_x->Mod_index == index))
+      if ((reg_x->Mod_name == module) && (reg_x->Mod_index == r_index))
 	return reg_x->reg_name;
     }
 
@@ -195,7 +195,7 @@ get_reg_name (unsigned char reg_code, type1 arg_pos)
     }
 
   memset (unres_reg_name, 0, 20);
-  sprintf (unres_reg_name, "%01x%01xh", index, module);
+  sprintf (unres_reg_name, "%01x%01xh", r_index, module);
 
   return unres_reg_name;
 }
diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c
index b8ef515..3941266 100644
--- a/opcodes/mcore-dis.c
+++ b/opcodes/mcore-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble Motorola M*Core instructions.
-   Copyright 1993, 1999, 2000, 2001, 2002, 2005, 2007
+   Copyright 1993, 1999, 2000, 2001, 2002, 2005, 2007, 2009
    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
@@ -94,7 +94,7 @@ print_insn_mcore (memaddr, info)
      struct disassemble_info *info;
 {
   unsigned char ibytes[4];
-  fprintf_ftype fprintf = info->fprintf_func;
+  fprintf_ftype print_func = info->fprintf_func;
   void *stream = info->stream;
   unsigned short inst;
   const mcore_opcode_info *op;
@@ -123,12 +123,12 @@ print_insn_mcore (memaddr, info)
       break;
 
   if (op->name == 0)
-    (*fprintf) (stream, ".short 0x%04x", inst);
+    (*print_func) (stream, ".short 0x%04x", inst);
   else
     {
       const char *name = grname[inst & 0x0F];
 
-      (*fprintf) (stream, "%s", op->name);
+      (*print_func) (stream, "%s", op->name);
 
       switch (op->opclass)
 	{
@@ -136,42 +136,42 @@ print_insn_mcore (memaddr, info)
 	  break;
 
 	case OT:
-	  (*fprintf) (stream, "\t%d", inst & 0x3);
+	  (*print_func) (stream, "\t%d", inst & 0x3);
 	  break;
 
 	case O1:
 	case JMP:
 	case JSR:
-	  (*fprintf) (stream, "\t%s", name);
+	  (*print_func) (stream, "\t%s", name);
 	  break;
 
 	case OC:
-	  (*fprintf) (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
+	  (*print_func) (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
 	  break;
 
 	case O1R1:
-	  (*fprintf) (stream, "\t%s, r1", name);
+	  (*print_func) (stream, "\t%s, r1", name);
 	  break;
 
 	case MULSH:
 	case O2:
-	  (*fprintf) (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]);
+	  (*print_func) (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]);
 	  break;
 
 	case X1:
-	  (*fprintf) (stream, "\tr1, %s", name);
+	  (*print_func) (stream, "\tr1, %s", name);
 	  break;
 
 	case OI:
-	  (*fprintf) (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1);
+	  (*print_func) (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1);
 	  break;
 
 	case RM:
-	  (*fprintf) (stream, "\t%s-r15, (r0)", name);
+	  (*print_func) (stream, "\t%s-r15, (r0)", name);
 	  break;
 
 	case RQ:
-	  (*fprintf) (stream, "\tr4-r7, (%s)", name);
+	  (*print_func) (stream, "\tr4-r7, (%s)", name);
 	  break;
 
 	case OB:
@@ -183,16 +183,16 @@ print_insn_mcore (memaddr, info)
 	case OMa:
 	case OMb:
 	case OMc:
-	  (*fprintf) (stream, "\t%s, %d", name, (inst >> 4) & 0x1F);
+	  (*print_func) (stream, "\t%s, %d", name, (inst >> 4) & 0x1F);
 	  break;
 
 	case I7:
-	  (*fprintf) (stream, "\t%s, %d", name, (inst >> 4) & 0x7F);
+	  (*print_func) (stream, "\t%s, %d", name, (inst >> 4) & 0x7F);
 	  break;
 
 	case LS:
-	  (*fprintf) (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
-		      name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
+	  (*print_func) (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
+			 name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
 	  break;
 
 	case BR:
@@ -202,7 +202,7 @@ print_insn_mcore (memaddr, info)
 	    if (inst & 0x400)
 	      val |= 0xFFFFFC00;
 
-	    (*fprintf) (stream, "\t0x%lx", (long)(memaddr + 2 + (val << 1)));
+	    (*print_func) (stream, "\t0x%lx", (long)(memaddr + 2 + (val << 1)));
 
 	    if (strcmp (op->name, "bsr") == 0)
 	      {
@@ -211,7 +211,7 @@ print_insn_mcore (memaddr, info)
 
 		if (info->print_address_func && val != 0)
 		  {
-		    (*fprintf) (stream, "\t// ");
+		    (*print_func) (stream, "\t// ");
 		    info->print_address_func (val, info);
 		  }
 	      }
@@ -222,9 +222,9 @@ print_insn_mcore (memaddr, info)
 	  {
 	    long val;
 	    val = (inst & 0x000F);
-	    (*fprintf) (stream, "\t%s, 0x%lx",
-			grname[(inst >> 4) & 0xF],
-			(long) (memaddr - (val << 1)));
+	    (*print_func) (stream, "\t%s, 0x%lx",
+			   grname[(inst >> 4) & 0xF],
+			   (long) (memaddr - (val << 1)));
 	  }
 	  break;
 
@@ -249,12 +249,12 @@ print_insn_mcore (memaddr, info)
 		| (ibytes[2] << 8) | (ibytes[3]);
 
 	    /* Removed [] around literal value to match ABI syntax 12/95.  */
-	    (*fprintf) (stream, "\t%s, 0x%lX", grname[(inst >> 8) & 0xF], val);
+	    (*print_func) (stream, "\t%s, 0x%lX", grname[(inst >> 8) & 0xF], val);
 
 	    if (val == 0)
-	      (*fprintf) (stream, "\t// from address pool at 0x%lx",
-			  (long) (memaddr + 2
-				  + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
+	      (*print_func) (stream, "\t// from address pool at 0x%lx",
+			     (long) (memaddr + 2
+				     + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
 	  }
 	  break;
 
@@ -279,18 +279,18 @@ print_insn_mcore (memaddr, info)
 		| (ibytes[2] << 8) | (ibytes[3]);
 
 	    /* Removed [] around literal value to match ABI syntax 12/95.  */
-	    (*fprintf) (stream, "\t0x%lX", val);
+	    (*print_func) (stream, "\t0x%lX", val);
 	    /* For jmpi/jsri, we'll try to get a symbol for the target.  */
 	    if (info->print_address_func && val != 0)
 	      {
-		(*fprintf) (stream, "\t// ");
+		(*print_func) (stream, "\t// ");
 		info->print_address_func (val, info);
 	      }
 	    else
 	      {
-		(*fprintf) (stream, "\t// from address pool at 0x%lx",
-			    (long) (memaddr + 2
-				    + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
+		(*print_func) (stream, "\t// from address pool at 0x%lx",
+			       (long) (memaddr + 2
+				       + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
 	      }
 	  }
 	  break;
@@ -302,13 +302,13 @@ print_insn_mcore (memaddr, info)
 	      "ee", "ee,ie", "ee,fe", "ee,fe,ie"
 	    };
 
-	    (*fprintf) (stream, "\t%s", fields[inst & 0x7]);
+	    (*print_func) (stream, "\t%s", fields[inst & 0x7]);
 	  }
 	  break;
 
 	default:
 	  /* If the disassembler lags the instruction set.  */
-	  (*fprintf) (stream, "\tundecoded operands, inst is 0x%04x", inst);
+	  (*print_func) (stream, "\tundecoded operands, inst is 0x%04x", inst);
 	  break;
 	}
     }
diff --git a/opcodes/mep-asm.c b/opcodes/mep-asm.c
index 294db36..40ef82b 100644
--- a/opcodes/mep-asm.c
+++ b/opcodes/mep-asm.c
@@ -633,7 +633,7 @@ expand_macro (arg *args, int narg, macro *mac)
   char *result = 0, *rescanned_result = 0;
   char *e = mac->expansion;
   char *mark = e;
-  int arg = 0;
+  int mac_arg = 0;
 
   /*  printf("expanding macro %s with %d args\n", mac->name, narg + 1); */
   while (*e)
@@ -644,9 +644,9 @@ expand_macro (arg *args, int narg, macro *mac)
 	  ((*(e + 1) - '1') <= narg))
 	{
 	  result = str_append (result, mark, e - mark);
-	  arg = (*(e + 1) - '1');
-	  /* printf("replacing `%d with %s\n", arg+1, args[arg].start); */
-	  result = str_append (result, args[arg].start, args[arg].len);
+	  mac_arg = (*(e + 1) - '1');
+	  /* printf("replacing `%d with %s\n", mac_arg+1, args[mac_arg].start); */
+	  result = str_append (result, args[mac_arg].start, args[mac_arg].len);
 	  ++e;
 	  mark = e+1;
 	}
@@ -678,8 +678,7 @@ expand_string (const char *in, int first_only)
   arg args[MAXARGS];
   int state = IN_TEXT;
   const char *mark = in;
-  macro *macro = 0;
-
+  macro *pmacro = NULL;
   char *expansion = 0;
   char *result = 0;
 
@@ -690,18 +689,18 @@ expand_string (const char *in, int first_only)
 	case IN_TEXT:
 	  if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) 
 	    {	      
-	      macro = lookup_macro (in + 1);
-	      if (macro)
+	      pmacro = lookup_macro (in + 1);
+	      if (pmacro)
 		{
 		  /* printf("entering state %d at '%s'...\n", state, in); */
 		  result = str_append (result, mark, in - mark);
 		  mark = in;
-		  in += 1 + strlen (macro->name);
+		  in += 1 + strlen (pmacro->name);
 		  while (*in == ' ') ++in;
 		  if (*in != '(')
 		    {
 		      state = IN_TEXT;		      
-		      macro = 0;
+		      pmacro = NULL;
 		    }
 		  else
 		    {
@@ -727,10 +726,10 @@ expand_string (const char *in, int first_only)
 		case ')':
 		  state = IN_TEXT;
 		  /* printf("entering state %d at '%s'...\n", state, in); */
-		  if (macro)
+		  if (pmacro)
 		    {
 		      expansion = 0;
-		      expansion = expand_macro (args, narg, macro);
+		      expansion = expand_macro (args, narg, pmacro);
 		      num_expansions++;
 		      if (expansion)
 			{
@@ -742,7 +741,7 @@ expand_string (const char *in, int first_only)
 		    {
 		      result = str_append (result, mark, in - mark);
 		    }
-		  macro = 0;
+		  pmacro = NULL;
 		  mark = in + 1;
 		  break;
 		case '(':
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
index b4723c2..1bbeead 100644
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -186,7 +186,7 @@ read_insn_microblaze (bfd_vma memaddr,
 int
 print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
 {
-  fprintf_ftype       fprintf = info->fprintf_func;
+  fprintf_ftype       print_func = info->fprintf_func;
   void *              stream = info->stream;
   unsigned long       inst, prev_inst;
   struct op_code_struct * op, *pop;
@@ -227,19 +227,19 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
   prev_insn_vma = curr_insn_vma;
 
   if (op->name == NULL)
-    fprintf (stream, ".short 0x%04x", inst);
+    print_func (stream, ".short 0x%04x", inst);
   else
     {
-      fprintf (stream, "%s", op->name);
+      print_func (stream, "%s", op->name);
 
       switch (op->inst_type)
 	{
         case INST_TYPE_RD_R1_R2:
-          fprintf (stream, "\t%s, %s, %s", get_field_rd (inst),
+          print_func (stream, "\t%s, %s, %s", get_field_rd (inst),
 		   get_field_r1(inst), get_field_r2 (inst));
           break;
         case INST_TYPE_RD_R1_IMM:
-	  fprintf (stream, "\t%s, %s, %s", get_field_rd (inst),
+	  print_func (stream, "\t%s, %s, %s", get_field_rd (inst),
 		   get_field_r1(inst), get_field_imm (inst));
 	  if (info->print_address_func && get_int_field_r1 (inst) == 0
 	      && info->symbol_at_address_func)
@@ -254,37 +254,37 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
 	        }
 	      if (immval > 0 && info->symbol_at_address_func (immval, info))
 		{
-	          fprintf (stream, "\t// ");
+	          print_func (stream, "\t// ");
 	          info->print_address_func (immval, info);
 	        }
 	    }
 	  break;
 	case INST_TYPE_RD_R1_IMM5:
-	  fprintf (stream, "\t%s, %s, %s", get_field_rd (inst),
+	  print_func (stream, "\t%s, %s, %s", get_field_rd (inst),
 	           get_field_r1(inst), get_field_imm5 (inst));
 	  break;
 	case INST_TYPE_RD_RFSL:
-	  fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_rfsl (inst));
+	  print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_rfsl (inst));
 	  break;
 	case INST_TYPE_R1_RFSL:
-	  fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_rfsl (inst));
+	  print_func (stream, "\t%s, %s", get_field_r1 (inst), get_field_rfsl (inst));
 	  break;
 	case INST_TYPE_RD_SPECIAL:
-	  fprintf (stream, "\t%s, %s", get_field_rd (inst),
+	  print_func (stream, "\t%s, %s", get_field_rd (inst),
 		   get_field_special (inst, op));
 	  break;
 	case INST_TYPE_SPECIAL_R1:
-	  fprintf (stream, "\t%s, %s", get_field_special (inst, op),
+	  print_func (stream, "\t%s, %s", get_field_special (inst, op),
 		   get_field_r1(inst));
 	  break;
 	case INST_TYPE_RD_R1:
-	  fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r1 (inst));
+	  print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r1 (inst));
 	  break;
 	case INST_TYPE_R1_R2:
-	  fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_r2 (inst));
+	  print_func (stream, "\t%s, %s", get_field_r1 (inst), get_field_r2 (inst));
 	  break;
 	case INST_TYPE_R1_IMM:
-	  fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_imm (inst));
+	  print_func (stream, "\t%s, %s", get_field_r1 (inst), get_field_imm (inst));
 	  /* The non-pc relative instructions are returns, which shouldn't
 	     have a label printed.  */
 	  if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET
@@ -301,18 +301,18 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
 	      immval += memaddr;
 	      if (immval > 0 && info->symbol_at_address_func (immval, info))
 		{
-	          fprintf (stream, "\t// ");
+	          print_func (stream, "\t// ");
 	          info->print_address_func (immval, info);
 	        }
 	      else
 		{
-	          fprintf (stream, "\t\t// ");
-	          fprintf (stream, "%x", immval);
+	          print_func (stream, "\t\t// ");
+	          print_func (stream, "%x", immval);
 	        }
 	    }
 	  break;
         case INST_TYPE_RD_IMM:
-	  fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_imm (inst));
+	  print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm (inst));
 	  if (info->print_address_func && info->symbol_at_address_func)
 	    {
 	    if (immfound)
@@ -327,13 +327,13 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
 	      immval += (int) memaddr;
 	    if (info->symbol_at_address_func (immval, info))
 	      {
-	        fprintf (stream, "\t// ");
+	        print_func (stream, "\t// ");
 	        info->print_address_func (immval, info);
 	      }
 	    }
 	  break;
         case INST_TYPE_IMM:
-	  fprintf (stream, "\t%s", get_field_imm (inst));
+	  print_func (stream, "\t%s", get_field_imm (inst));
 	  if (info->print_address_func && info->symbol_at_address_func
 	      && op->instr != imm)
 	    {
@@ -349,41 +349,41 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
 	        immval += (int) memaddr;
 	      if (immval > 0 && info->symbol_at_address_func (immval, info))
 		{
-	          fprintf (stream, "\t// ");
+	          print_func (stream, "\t// ");
 	          info->print_address_func (immval, info);
 	        }
 	      else if (op->inst_offset_type == INST_PC_OFFSET)
 		{
-	          fprintf (stream, "\t\t// ");
-	          fprintf (stream, "%x", immval);
+	          print_func (stream, "\t\t// ");
+	          print_func (stream, "%x", immval);
 	        }
 	    }
 	  break;
         case INST_TYPE_RD_R2:
-	  fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst));
+	  print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst));
 	  break;
 	case INST_TYPE_R2:
-	  fprintf (stream, "\t%s", get_field_r2 (inst));
+	  print_func (stream, "\t%s", get_field_r2 (inst));
 	  break;
 	case INST_TYPE_R1:
-	  fprintf (stream, "\t%s", get_field_r1 (inst));
+	  print_func (stream, "\t%s", get_field_r1 (inst));
 	  break;
 	case INST_TYPE_RD_R1_SPECIAL:
-	  fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst));
+	  print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst));
 	  break;
 	case INST_TYPE_RD_IMM15:
-	  fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst));
+	  print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst));
 	  break;
 	/* For tuqula instruction */
 	case INST_TYPE_RD:
-	  fprintf (stream, "\t%s", get_field_rd (inst));
+	  print_func (stream, "\t%s", get_field_rd (inst));
 	  break;
 	case INST_TYPE_RFSL:
-	  fprintf (stream, "\t%s", get_field_rfsl (inst));
+	  print_func (stream, "\t%s", get_field_rfsl (inst));
 	  break;
 	default:
 	  /* If the disassembler lags the instruction set.  */
-	  fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
+	  print_func (stream, "\tundecoded operands, inst is 0x%04x", inst);
 	  break;
 	}
     }
@@ -418,7 +418,7 @@ get_insn_microblaze (long inst,
 }
 
 enum microblaze_instr
-microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *imm)
+microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *immed)
 {
   enum microblaze_instr op;
   bfd_boolean t1;
@@ -430,7 +430,7 @@ microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *imm)
   *ra = (insn & RA_MASK) >> RA_LOW;
   *rb = (insn & RB_MASK) >> RB_LOW;
   t3 = (insn & IMM_MASK) >> IMM_LOW;
-  *imm = (int) t3;
+  *immed = (int) t3;
   return (op);
 }
 
diff --git a/opcodes/mmix-dis.c b/opcodes/mmix-dis.c
index 9ca845f..22db268 100644
--- a/opcodes/mmix-dis.c
+++ b/opcodes/mmix-dis.c
@@ -73,7 +73,7 @@ static bfd_boolean
 initialize_mmix_dis_info (struct disassemble_info *info)
 {
   struct mmix_dis_info *minfop = malloc (sizeof (struct mmix_dis_info));
-  int i;
+  long i;
 
   if (minfop == NULL)
     return FALSE;
@@ -98,7 +98,6 @@ initialize_mmix_dis_info (struct disassemble_info *info)
 	  long symsize = bfd_get_symtab_upper_bound (abfd);
 	  asymbol **syms = malloc (symsize);
 	  long nsyms;
-	  long i;
 
 	  if (syms == NULL)
 	    {
@@ -125,7 +124,7 @@ initialize_mmix_dis_info (struct disassemble_info *info)
   for (i = 0; i < 256; i++)
     if (minfop->reg_name[i] == NULL)
       {
-	sprintf (minfop->basic_reg_name[i], "$%d", i);
+	sprintf (minfop->basic_reg_name[i], "$%ld", i);
 	minfop->reg_name[i] = minfop->basic_reg_name[i];
       }
 
diff --git a/opcodes/ns32k-dis.c b/opcodes/ns32k-dis.c
index e96bdf4..ed6e165 100644
--- a/opcodes/ns32k-dis.c
+++ b/opcodes/ns32k-dis.c
@@ -1,6 +1,6 @@
 /* Print National Semiconductor 32000 instructions.
-   Copyright 1986, 1988, 1991, 1992, 1994, 1998, 2001, 2002, 2005, 2007
-   Free Software Foundation, Inc.
+   Copyright 1986, 1988, 1991, 1992, 1994, 1998, 2001, 2002, 2005, 2007,
+   2009  Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
@@ -466,7 +466,6 @@ print_insn_arg (int d,
   int Ivalue;
   int addr_mode;
   int disp1, disp2;
-  int index;
   int size;
 
   switch (d)
@@ -616,17 +615,17 @@ print_insn_arg (int d,
 	case 0x1d:
 	case 0x1e:
 	case 0x1f:
-	  /* Scaled index basemode[R0 -- R7:B,W,D,Q].  */
-	  index = bit_extract (buffer, index_offset - 8, 3);
-	  print_insn_arg (d, index_offset, aoffsetp, buffer, addr,
-			  result, 0);
 	  {
+	    int bit_index;
 	    static const char *ind = "bwdq";
 	    char *off;
-
+	    
+	    /* Scaled index basemode[R0 -- R7:B,W,D,Q].  */
+	    bit_index = bit_extract (buffer, index_offset - 8, 3);
+	    print_insn_arg (d, index_offset, aoffsetp, buffer, addr,
+			    result, 0);
 	    off = result + strlen (result);
-	    sprintf (off, "[r%d:%c]", index,
-		     ind[addr_mode & 3]);
+	    sprintf (off, "[r%d:%c]", bit_index, ind[addr_mode & 3]);
 	  }
 	  break;
 	}
diff --git a/opcodes/or32-opc.c b/opcodes/or32-opc.c
index 24ab5cf..ff624e7 100644
--- a/opcodes/or32-opc.c
+++ b/opcodes/or32-opc.c
@@ -345,7 +345,7 @@ const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct o
 /* Calculates instruction length in bytes. Always 4 for OR32.  */
 
 int
-insn_len (int insn_index ATTRIBUTE_UNUSED)
+insn_len (int i_index ATTRIBUTE_UNUSED)
 {
   return 4;
 }
@@ -409,10 +409,10 @@ insn_index (char *insn)
 }
 
 const char *
-insn_name (int index)
+insn_name (int op_index)
 {
-  if (index >= 0 && index < (int) or32_num_opcodes)
-    return or32_opcodes[index].name;
+  if (op_index >= 0 && op_index < (int) or32_num_opcodes)
+    return or32_opcodes[op_index].name;
   else
     return "???";
 }
@@ -985,12 +985,12 @@ or32_print_immediate (char param_ch, char *encoding, unsigned long insn)
 int
 disassemble_insn (unsigned long insn)
 {
-  int index;
-  index = insn_decode (insn);
+  int op_index;
+  op_index = insn_decode (insn);
 
-  if (index >= 0)
+  if (op_index >= 0)
     {
-      struct or32_opcode const *opcode = &or32_opcodes[index];
+      struct or32_opcode const *opcode = &or32_opcodes[op_index];
       char *s;
 
       sprintf (disassembled, "%s ", opcode->name);
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index 986e4b5..b9eeb79 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -196,8 +196,6 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
 	  separator = 0;
 	  for (opindex = opcode->operands; *opindex != 0; opindex++)
 	    {
-	      unsigned int value;
-
 	      operand = s390_operands + *opindex;
 	      value = s390_extract_operand (buffer, operand);
 
diff --git a/opcodes/sh64-dis.c b/opcodes/sh64-dis.c
index edb7382..60963e7 100644
--- a/opcodes/sh64-dis.c
+++ b/opcodes/sh64-dis.c
@@ -195,8 +195,6 @@ print_insn_shmedia (bfd_vma memaddr, struct disassemble_info *info)
      can get as .byte:s.  */
   if (status != 0)
     {
-      int i;
-
       for (i = 0; i < 3; i++)
 	{
 	  status = info->read_memory_func (memaddr + i, insn, 1, info);
diff --git a/opcodes/spu-dis.c b/opcodes/spu-dis.c
index eae9503..3e6a762 100644
--- a/opcodes/spu-dis.c
+++ b/opcodes/spu-dis.c
@@ -53,7 +53,7 @@ init_spu_disassemble (void)
 static const struct spu_opcode *
 get_index_for_opcode (unsigned int insn)
 {
-  const struct spu_opcode *index;
+  const struct spu_opcode *op_index;
   unsigned int opcode = insn >> (32-11);
 
   /* Init the table.  This assumes that element 0/opcode 0 (currently
@@ -61,28 +61,28 @@ get_index_for_opcode (unsigned int insn)
   if (spu_disassemble_table[0] == 0)
     init_spu_disassemble ();
 
-  if ((index = spu_disassemble_table[opcode & 0x780]) != 0
-      && index->insn_type == RRR)
-    return index;
+  if ((op_index = spu_disassemble_table[opcode & 0x780]) != 0
+      && op_index->insn_type == RRR)
+    return op_index;
 
-  if ((index = spu_disassemble_table[opcode & 0x7f0]) != 0
-      && (index->insn_type == RI18 || index->insn_type == LBT))
-    return index;
+  if ((op_index = spu_disassemble_table[opcode & 0x7f0]) != 0
+      && (op_index->insn_type == RI18 || op_index->insn_type == LBT))
+    return op_index;
 
-  if ((index = spu_disassemble_table[opcode & 0x7f8]) != 0
-      && index->insn_type == RI10)
-    return index;
+  if ((op_index = spu_disassemble_table[opcode & 0x7f8]) != 0
+      && op_index->insn_type == RI10)
+    return op_index;
 
-  if ((index = spu_disassemble_table[opcode & 0x7fc]) != 0
-      && (index->insn_type == RI16))
-    return index;
+  if ((op_index = spu_disassemble_table[opcode & 0x7fc]) != 0
+      && (op_index->insn_type == RI16))
+    return op_index;
 
-  if ((index = spu_disassemble_table[opcode & 0x7fe]) != 0
-      && (index->insn_type == RI8))
-    return index;
+  if ((op_index = spu_disassemble_table[opcode & 0x7fe]) != 0
+      && (op_index->insn_type == RI8))
+    return op_index;
 
-  if ((index = spu_disassemble_table[opcode & 0x7ff]) != 0)
-    return index;
+  if ((op_index = spu_disassemble_table[opcode & 0x7ff]) != 0)
+    return op_index;
 
   return 0;
 }
@@ -97,7 +97,7 @@ print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
   int hex_value;
   int status;
   unsigned int insn;
-  const struct spu_opcode *index;
+  const struct spu_opcode *op_index;
   enum spu_insns tag;
 
   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
@@ -109,9 +109,9 @@ print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
 
   insn = bfd_getb32 (buffer);
 
-  index = get_index_for_opcode (insn);
+  op_index = get_index_for_opcode (insn);
 
-  if (index == 0)
+  if (op_index == 0)
     {
       (*info->fprintf_func) (info->stream, ".long 0x%x", insn);
     }
@@ -119,8 +119,8 @@ print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
     {
       int i;
       int paren = 0;
-      tag = (enum spu_insns)(index - spu_opcodes);
-      (*info->fprintf_func) (info->stream, "%s", index->mnemonic);
+      tag = (enum spu_insns)(op_index - spu_opcodes);
+      (*info->fprintf_func) (info->stream, "%s", op_index->mnemonic);
       if (tag == M_BI || tag == M_BISL || tag == M_IRET || tag == M_BISLED
 	  || tag == M_BIHNZ || tag == M_BIHZ || tag == M_BINZ || tag == M_BIZ
           || tag == M_SYNC || tag == M_HBR)
@@ -133,12 +133,12 @@ print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
 	  if (fb & 0x10)
 	    (*info->fprintf_func) (info->stream, "e");
 	}
-      if (index->arg[0] != 0)
+      if (op_index->arg[0] != 0)
 	(*info->fprintf_func) (info->stream, "\t");
       hex_value = 0;
-      for (i = 1;  i <= index->arg[0]; i++)
+      for (i = 1;  i <= op_index->arg[0]; i++)
 	{
-	  int arg = index->arg[i];
+	  int arg = op_index->arg[i];
 	  if (arg != A_P && !paren && i > 1)
 	    (*info->fprintf_func) (info->stream, ",");
 
diff --git a/opcodes/tic30-dis.c b/opcodes/tic30-dis.c
index d4ece40..c6d0e3e 100644
--- a/opcodes/tic30-dis.c
+++ b/opcodes/tic30-dis.c
@@ -275,7 +275,7 @@ get_indirect_operand (unsigned short fragment,
 static int
 cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat)
 {
-  unsigned long exp, sign, mant;
+  unsigned long exponent, sign, mant;
   union
   {
     unsigned long l;
@@ -292,16 +292,16 @@ cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat)
 	  tmsfloat = (long) tmsfloat >> 4;
 	}
     }
-  exp = tmsfloat & 0xFF000000;
-  if (exp == 0x80000000)
+  exponent = tmsfloat & 0xFF000000;
+  if (exponent == 0x80000000)
     {
       *ieeefloat = 0.0;
       return 1;
     }
-  exp += 0x7F000000;
+  exponent += 0x7F000000;
   sign = (tmsfloat & 0x00800000) << 8;
   mant = tmsfloat & 0x007FFFFF;
-  if (exp == 0xFF000000)
+  if (exponent == 0xFF000000)
     {
       if (mant == 0)
 	*ieeefloat = ERANGE;
@@ -318,18 +318,18 @@ cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat)
 #endif
       return 1;
     }
-  exp >>= 1;
+  exponent >>= 1;
   if (sign)
     {
       mant = (~mant) & 0x007FFFFF;
       mant += 1;
-      exp += mant & 0x00800000;
-      exp &= 0x7F800000;
+      exponent += mant & 0x00800000;
+      exponent &= 0x7F800000;
       mant &= 0x007FFFFF;
     }
   if (tmsfloat == 0x80000000)
-    sign = mant = exp = 0;
-  tmsfloat = sign | exp | mant;
+    sign = mant = exponent = 0;
+  tmsfloat = sign | exponent | mant;
   val.l = tmsfloat;
   *ieeefloat = val.f;
   return 1;