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| author | Jan Beulich <jbeulich@novell.com> | 2014-10-21 09:56:38 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2014-10-21 09:56:38 +0200 |
| commit | 12e87fac5c760b04eed4f5a5948c2dfd6ec8f6d8 (patch) | |
| tree | a53ccf19107b20039ae884b69ef3e3d0936f272d /opcodes | |
| parent | 28f013d5cb2b60882c73f10eedb26fa5b3b15b2f (diff) | |
| download | fsf-binutils-gdb-12e87fac5c760b04eed4f5a5948c2dfd6ec8f6d8.zip fsf-binutils-gdb-12e87fac5c760b04eed4f5a5948c2dfd6ec8f6d8.tar.gz fsf-binutils-gdb-12e87fac5c760b04eed4f5a5948c2dfd6ec8f6d8.tar.bz2 | |
ppc: enable msgclr and msgsnd on Power8
According to my reading of the spec it was an oversight for them to
not having got enabled when Power8 support got added.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 93d474a..49fc81d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2014-10-21 Jan Beulich <jbeulich@suse.com> + + * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8. + 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index a5cfe1a..bcc0ca0 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4653,7 +4653,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}}, +{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}}, {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, @@ -4700,7 +4700,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, -{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}}, +{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}}, {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, |