diff options
| author | Alan Modra <amodra@gmail.com> | 2004-04-08 12:41:56 +0000 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2004-04-08 12:41:56 +0000 |
| commit | 5d4eeb361c60e748794eb88ca38b8d6ac569ab33 (patch) | |
| tree | 92d177e2c4b055d7ebaee5b49748ff50325e3dbd /opcodes | |
| parent | d9c9896fcc682d867284e38c9de28b2fae3a31c8 (diff) | |
| download | fsf-binutils-gdb-5d4eeb361c60e748794eb88ca38b8d6ac569ab33.zip fsf-binutils-gdb-5d4eeb361c60e748794eb88ca38b8d6ac569ab33.tar.gz fsf-binutils-gdb-5d4eeb361c60e748794eb88ca38b8d6ac569ab33.tar.bz2 | |
Merge from mainline
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 21 | ||||
| -rw-r--r-- | opcodes/po/POTFILES.in | 1 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 15 |
3 files changed, 33 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 63c17a5..643e508 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,25 @@ +2004-04-08 Alan Modra <amodra@bigpond.net.au> + + Apply from mainline. + 2004-02-25 Aldy Hernandez <aldyh@redhat.com> + * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst. + + 2004-02-20 Aldy Hernandez <aldyh@redhat.com> + * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat. + + 2004-02-20 Aldy Hernandez <aldyh@redhat.com> + * ppc-opc.c (powerpc_opcodes): Add m*ivor35. + + 2004-02-20 Aldy Hernandez <aldyh@redhat.com> + * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34, + mtivor32, mtivor33, mtivor34. + + 2004-02-19 Aldy Hernandez <aldyh@redhat.com> + * ppc-opc.c (powerpc_opcodes): Add mfmcar. + 2004-03-15 Aldy Hernandez <aldyh@redhat.com> - * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg. + * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg. 2004-03-16 Alan Modra <amodra@bigpond.net.au> diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in index f16a87b..333c612 100644 --- a/opcodes/po/POTFILES.in +++ b/opcodes/po/POTFILES.in @@ -18,6 +18,7 @@ d30v-dis.c d30v-opc.c disassemble.c dis-buf.c +dis-init.c dlx-dis.c fr30-asm.c fr30-desc.c diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index c513cb8..36fe454 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -3480,7 +3480,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, -{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } }, +{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } }, { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, @@ -3514,7 +3514,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, -{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } }, +{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, @@ -3691,6 +3691,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } }, { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } }, +{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } }, +{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } }, +{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } }, +{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } }, { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, @@ -3700,10 +3704,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, +{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, +{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, @@ -3997,6 +4002,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } }, { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } }, { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } }, +{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } }, +{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } }, +{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } }, +{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } }, { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |