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| author | David S. Miller <davem@redhat.com> | 2011-08-05 16:52:50 +0000 |
|---|---|---|
| committer | David S. Miller <davem@redhat.com> | 2011-08-05 16:52:50 +0000 |
| commit | ea783ef3a075b7581b93615f8aec39490d272b4f (patch) | |
| tree | 8bf5a133e8a14cf864ba46b1799241d0268c9744 /opcodes/sparc-dis.c | |
| parent | d6c10e950e91d34b7193c43395c695b0fd51400f (diff) | |
| download | fsf-binutils-gdb-ea783ef3a075b7581b93615f8aec39490d272b4f.zip fsf-binutils-gdb-ea783ef3a075b7581b93615f8aec39490d272b4f.tar.gz fsf-binutils-gdb-ea783ef3a075b7581b93615f8aec39490d272b4f.tar.bz2 | |
include/opcode/
* sparc.h: Document new format codes '4', '5', and '('.
(OPF_LOW4, RS3): New macros.
opcodes/
* sparc-dis.c (v9a_ast_reg_names): Add "cps".
(X_RS3): New macro.
(print_insn_sparc): Handle '4', '5', and '(' format codes.
Accept %asr numbers below 28.
* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
instructions.
gas/
* config/tc-sparc.c (v9a_asr_table): Add "cps".
(sparc_ip): Handle '4', '5' and '(' format codes.
gas/testsuite
* gas/sparc/hpcvis3.d: New test.
* gas/sparc/hpcvis3.s: New test source.
* gas/sparc/sparc.exp: Run new test.
Diffstat (limited to 'opcodes/sparc-dis.c')
| -rw-r--r-- | opcodes/sparc-dis.c | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c index 8dec272..b7f0cc2 100644 --- a/opcodes/sparc-dis.c +++ b/opcodes/sparc-dis.c @@ -108,7 +108,8 @@ static char *v9_hpriv_reg_names[] = static char *v9a_asr_reg_names[] = { "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", - "softint", "tick_cmpr", "stick", "stick_cmpr" + "softint", "tick_cmpr", "stick", "stick_cmpr", "resv26", + "resv27", "cps" }; /* Macros used to extract instruction fields. Not all fields have @@ -119,6 +120,7 @@ static char *v9a_asr_reg_names[] = #define X_LDST_I(i) (((i) >> 13) & 1) #define X_ASI(i) (((i) >> 5) & 0xff) #define X_RS2(i) (((i) >> 0) & 0x1f) +#define X_RS3(i) (((i) >> 9) & 0x1f) #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) #define X_DISP22(i) (((i) >> 0) & 0x3fffff) @@ -634,6 +636,13 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info) fregx (X_RS2 (insn)); break; + case '4': + freg (X_RS3 (insn)); + break; + case '5': /* Double/even. */ + fregx (X_RS3 (insn)); + break; + case 'g': freg (X_RD (insn)); break; @@ -814,7 +823,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info) break; case '/': - if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) + if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28) (*info->fprintf_func) (stream, "%%reserved"); else (*info->fprintf_func) (stream, "%%%s", @@ -822,7 +831,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info) break; case '_': - if (X_RD (insn) < 16 || X_RD (insn) > 25) + if (X_RD (insn) < 16 || X_RD (insn) > 28) (*info->fprintf_func) (stream, "%%reserved"); else (*info->fprintf_func) (stream, "%%%s", @@ -882,6 +891,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info) (*info->fprintf_func) (stream, "%%fsr"); break; + case '(': + (*info->fprintf_func) (stream, "%%efsr"); + break; + case 'p': (*info->fprintf_func) (stream, "%%psr"); break; |