Make RL78 disassembler and simulator respect ISA for mul/div

[gas]
	* config/rl78-defs.h (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.
	* config/rl78-parse.y (ISA_G10): New.
	(ISA_G13): New.
	(ISA_G14): New.
	(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
	* config/tc-rl78.c (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.

[gdb]
	* rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to
	rl78_decode_opcode

[include]
	* dis-asm.h (print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.
	* opcode/rl78.h (RL78_Dis_Isa): New.
	(rl78_decode_opcode): Add ISA parameter.

[opcodes]
	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

[sim]
	* rl78/cpu.c (g14_multiply): New.
	* rl78/cpu.h (g14_multiply): New.
	* rl78/load.c (rl78_load): Decode ISA completely.
	* rl78/main.c (main): Expand -M to include other ISAs.
	* rl78/rl78.c (decode_opcode): Decode based on ISA.
	* rl78/trace.c (rl78_disasm_fn): New.
	(sim_disasm_init): Reset it.
	(sim_disasm_one): Get correct disassembler for ISA.

1 files changed, 46 insertions, 3 deletions

diff --git a/opcodes/rl78-dis.c b/opcodes/rl78-dis.c
index a2298ce..25d0baf 100644
--- a/opcodes/rl78-dis.c
+++ b/opcodes/rl78-dis.c
@@ -24,8 +24,10 @@
 #include <stdio.h>
 
 #include "bfd.h"
+#include "elf-bfd.h"
 #include "dis-asm.h"
 #include "opcode/rl78.h"
+#include "elf/rl78.h"
 
 #define DEBUG_SEMANTICS 0
 
@@ -80,8 +82,8 @@ indirect_type (int t)
     }
 }
 
-int
-print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
+static int
+print_insn_rl78_common (bfd_vma addr, disassemble_info * dis, RL78_Dis_Isa isa)
 {
   int rv;
   RL78_Data rl78_data;
@@ -94,7 +96,7 @@ print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
   rl78_data.pc = addr;
   rl78_data.dis = dis;
 
-  rv = rl78_decode_opcode (addr, &opcode, rl78_get_byte, &rl78_data);
+  rv = rl78_decode_opcode (addr, &opcode, rl78_get_byte, &rl78_data, isa);
 
   dis->bytes_per_line = 10;
 
@@ -327,3 +329,44 @@ print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
 
   return rv;
 }
+
+int
+print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
+{
+  return print_insn_rl78_common (addr, dis, RL78_ISA_DEFAULT);
+}
+
+int
+print_insn_rl78_g10 (bfd_vma addr, disassemble_info * dis)
+{
+  return print_insn_rl78_common (addr, dis, RL78_ISA_G10);
+}
+
+int
+print_insn_rl78_g13 (bfd_vma addr, disassemble_info * dis)
+{
+  return print_insn_rl78_common (addr, dis, RL78_ISA_G13);
+}
+
+int
+print_insn_rl78_g14 (bfd_vma addr, disassemble_info * dis)
+{
+  return print_insn_rl78_common (addr, dis, RL78_ISA_G14);
+}
+
+disassembler_ftype
+rl78_get_disassembler (bfd *abfd)
+{
+  int cpu = abfd->tdata.elf_obj_data->elf_header->e_flags & E_FLAG_RL78_CPU_MASK;
+  switch (cpu)
+    {
+    case E_FLAG_RL78_G10:
+      return print_insn_rl78_g10;
+    case E_FLAG_RL78_G13:
+      return print_insn_rl78_g13;
+    case E_FLAG_RL78_G14:
+      return print_insn_rl78_g14;
+    default:
+      return print_insn_rl78;
+    }
+}