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authorRichard Sandiford <rdsandiford@googlemail.com>2001-08-10 16:22:08 +0000
committerRichard Sandiford <rdsandiford@googlemail.com>2001-08-10 16:22:08 +0000
commitd98bb281e84ba33e1e19f67319f01e19c9c9c8e3 (patch)
treebecda1116986bd153e9194c62e584392d2262dee /opcodes/mips-opc.c
parenta58ec95a7edf6346fcf46acc0f66d368ab64d34e (diff)
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* mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32
argument. * mips-opc.c (G6): Undefine. (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro as the first "move" alternative.
Diffstat (limited to 'opcodes/mips-opc.c')
-rw-r--r--opcodes/mips-opc.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 3028b99..ba4038b 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -96,8 +96,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
#define G3 (I4 \
)
-#define G6 INSN_GP32
-
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
@@ -121,7 +119,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
-{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1|G6 },/* or */
+{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 },
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */