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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-12 00:46:45 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-12 00:48:19 +0100 |
| commit | 99e2d67a0edd1a8feca82036feb93709fee488fa (patch) | |
| tree | 4e3f21a09ea6bb0e6775932390b1de07b2314563 /opcodes/micromips-opc.c | |
| parent | f2c29a169242d0c564afb46ecaf160422b28bfbb (diff) | |
| download | fsf-binutils-gdb-99e2d67a0edd1a8feca82036feb93709fee488fa.zip fsf-binutils-gdb-99e2d67a0edd1a8feca82036feb93709fee488fa.tar.gz fsf-binutils-gdb-99e2d67a0edd1a8feca82036feb93709fee488fa.tar.bz2 | |
MIPS/opcodes: Mark descriptive SYNC mnemonics as aliases
Following the way how descriptive SYNC mnemonics have been defined in
the architecture[1][2] mark them as aliases, so that the generic SYNC
instruction can be alternatively disassembled along with its immediate
operand, as noted in the documents referred.
References:
[1] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Table 4.7 "Encodings of the
Bits[10:6] of the SYNC instruction; the SType Field", p. 305
[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Table 5.28 "Encodings of the
Bits[10:6] of the SYNC instruction; the SType Field", p. 481
opcodes/
* mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
"syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
"sync_rmb" and "sync_wmb" as aliases.
* micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
gas/
* testsuite/gas/mips/mips32r2-sync-1.d: New test.
* testsuite/gas/mips/micromips@mips32r2-sync-1.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
Diffstat (limited to 'opcodes/micromips-opc.c')
| -rw-r--r-- | opcodes/micromips-opc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index d47e1e2..dcd235f 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -1064,11 +1064,11 @@ const struct mips_opcode micromips_opcodes[] = {"invalidate", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* same */ {"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, {"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I1, 0, 0 }, -{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, +{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, {"sync", "", 0x00006b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, {"sync", "1", 0x00006b7c, 0xffe0ffff, NODS, 0, I1, 0, 0 }, {"synci", "o(b)", 0x42000000, 0xffe00000, RD_2|SM, 0, I1, 0, 0 }, |