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author | Maciej W. Rozycki <macro@linux-mips.org> | 2013-06-25 18:02:34 +0000 |
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committer | Maciej W. Rozycki <macro@linux-mips.org> | 2013-06-25 18:02:34 +0000 |
commit | 833794fc12d98139fc33f6b0b85feb03471007b7 (patch) | |
tree | a7c2fa06414c50f6e0bb252a7f5593c0db4c2ff8 /opcodes/micromips-opc.c | |
parent | 6e2048d3e3a50472e73d74d97ae031741464b756 (diff) | |
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bfd/
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype.
* elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member.
(STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros.
(MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise.
(MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise.
(micromips_insn32_o32_exec_plt0_entry): New variable.
(micromips_insn32_o32_exec_plt_entry): Likewise.
(_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode.
(mips_elf_estimate_stub_size): Likewise.
(_bfd_mips_elf_size_dynamic_sections): Likewise.
(_bfd_mips_elf_finish_dynamic_symbol): Likewise.
(mips_finish_exec_plt): Likewise.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_insn32): New function.
(_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT.
gas/
* config/tc-mips.c (mips_set_options): Add insn32 member.
(mips_opts): Initialize it.
(NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
(options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
(md_longopts): Add "minsn32" and "mno-insn32" options.
(is_size_valid): Handle insn32 mode.
(md_assemble): Pass instruction string down to macro.
(brk_fmt): Add second dimension and insn32 mode initializers.
(mfhl_fmt): Likewise.
(BRK_FMT, MFHL_FMT): Handle insn32 mode.
(macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
(macro_build_jalr, move_register): Handle insn32 mode.
(macro_build_branch_rs): Likewise.
(macro): Handle insn32 mode.
<M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
(mips_ip): Handle insn32 mode.
(md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
(s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
(mips_handle_align): Handle insn32 mode.
(md_show_usage): Add -minsn32 and -mno-insn32.
* doc/as.texinfo (Target MIPS options): Add -minsn32 and
-mno-insn32 options.
(-minsn32, -mno-insn32): New options.
* doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
options.
(MIPS assembly options): New node. Document .set insn32 and
.set noinsn32.
(MIPS-Dependent): List the new node.
gas/testsuite/
* gas/mips/micromips-insn32.d: New test.
* gas/mips/micromips-noinsn32.d: Likewise.
* gas/mips/micromips.l: Rename to...
* gas/mips/micromips-warn.l: ... this.
* gas/mips/micromips.d: Update accordingly.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New list test.
* gas/mips/micromips.s: Add conditionals.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
values.
ld/
* emultempl/mipself.em (insn32): New variable.
(mips_create_output_section_statements): Handle insn32 mode.
(PARSE_AND_LIST_PROLOGUE): New macro.
(PARSE_AND_LIST_LONGOPTS): Likewise.
(PARSE_AND_LIST_OPTIONS): Likewise.
* gen-doc.texi: Set MIPS.
* ld.texinfo: Likewise.
(Options specific to MIPS targets): New section.
(ld and MIPS family): New node.
(Top, Machine Dependent): List the new node.
opcodes/
* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
and "movep" macros.
Diffstat (limited to 'opcodes/micromips-opc.c')
-rw-r--r-- | opcodes/micromips-opc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index 34e7b12..c583d7a 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -548,7 +548,13 @@ const struct mips_opcode micromips_opcodes[] = {"jr", "s", 0x00000f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jalr */ {"jrs", "s", 0x00004f3c, 0xffe0ffff, UBD|RD_s, BD16, I1 }, /* jalrs */ {"jraddiusp", "mP", 0x4700, 0xffe0, NODS, UBR|RD_31|WR_sp|RD_sp, I1 }, +/* This macro is after the real instruction so that it only matches with + -minsn32. */ +{"jraddiusp", "mP", 0, (int) M_JRADDIUSP, INSN_MACRO, 0, I1 }, {"jrc", "mj", 0x45a0, 0xffe0, NODS, UBR|RD_mj, I1 }, +/* This macro is after the real instruction so that it only matches with + -minsn32. */ +{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1 }, {"jr.hb", "s", 0x00001f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jalr.hb */ {"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, UBD|RD_s, BD16, I1 }, /* jalrs.hb */ {"j", "mj", 0x4580, 0xffe0, UBD, RD_mj, I1 }, /* jr */ @@ -704,6 +710,9 @@ const struct mips_opcode micromips_opcodes[] = {"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 }, {"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 }, {"movep", "mh,mi,mm,mn", 0x8400, 0xfc01, NODS, WR_mhi|RD_mmn, I1 }, +/* This macro is after the real instruction so that it only matches with + -minsn32. */ +{"movep", "mh,mi,mm,mn", 0, (int) M_MOVEP, INSN_MACRO, 0, I1 }, {"movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_t|RD_s|RD_CC|FP_S|FP_D, 0, I1 }, {"movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 }, {"movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_T|RD_S|RD_CC|FP_S, 0, I1 }, |