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| author | Chao-ying Fu <fu@mips.com> | 2013-10-07 18:02:47 +0000 |
|---|---|---|
| committer | Chao-ying Fu <fu@mips.com> | 2013-10-07 18:02:47 +0000 |
| commit | 45099dfad225994154148d0fef2ff98f9e0d4e34 (patch) | |
| tree | 3e2bf3fa65ada4f8c50c0616091f04214a98b1c9 /opcodes/micromips-opc.c | |
| parent | 54de2ea6586f288d90aee0fb8eae68e3c55dec03 (diff) | |
| download | fsf-binutils-gdb-45099dfad225994154148d0fef2ff98f9e0d4e34.zip fsf-binutils-gdb-45099dfad225994154148d0fef2ff98f9e0d4e34.tar.gz fsf-binutils-gdb-45099dfad225994154148d0fef2ff98f9e0d4e34.tar.bz2 | |
2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
Diffstat (limited to 'opcodes/micromips-opc.c')
| -rw-r--r-- | opcodes/micromips-opc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index fa6efb5..c5733d4 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -586,12 +586,12 @@ const struct mips_opcode micromips_opcodes[] = {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3, 0, 0 }, {"dmfc0", "t,G", 0x580000fc, 0xfc00ffff, WR_1|RD_C0, 0, I3, 0, 0 }, {"dmfc0", "t,G,H", 0x580000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I3, 0, 0 }, -{"dmfgc0", "t,G", 0x580000e7, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, -{"dmfgc0", "t,G,H", 0x580000e7, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, +{"dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, +{"dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, {"dmtc0", "t,G", 0x580002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, {"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, -{"dmtgc0", "t,G", 0x580002e7, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, -{"dmtgc0", "t,G,H", 0x580002e7, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, +{"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, +{"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, {"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I3, 0, 0 }, {"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I3, 0, 0 }, {"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S, 0, I3, 0, 0 }, |