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authorMichael Eager <eager@eagercon.com>2012-11-21 17:54:11 +0000
committerMichael Eager <eager@eagercon.com>2012-11-21 17:54:11 +0000
commitabe9f67d45d38ee87b501da03a9b9778d31095fb (patch)
tree1c8994d0dcc2f7b674791ab5d41bccd707a4cd25 /opcodes/microblaze-opc.h
parent0db4b3260cfc1818dba17ee53bb8e6ca6fdefecc (diff)
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Add swap byte (swapb) and swap halfword (swaph) opcodes.
binutils/opcodes * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES. * microblaze-opcm.h (microblaze_instr): Likewise binutils/gas/testsuite * gas/microblaze/allinsn.s: Add swapb, swaph * gas/microblaze/allinsn.d: Likewise
Diffstat (limited to 'opcodes/microblaze-opc.h')
-rw-r--r--opcodes/microblaze-opc.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 0447fc5..404985b 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -101,7 +101,7 @@
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
-#define MAX_OPCODES 287
+#define MAX_OPCODES 289
struct op_code_struct
{
@@ -402,6 +402,8 @@ struct op_code_struct
{"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
{"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
{"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
+ {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
+ {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
{"", 0, 0, 0, 0, 0, 0, 0, 0},
};