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| author | Jan Beulich <jbeulich@novell.com> | 2017-12-18 09:34:00 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2017-12-18 09:34:00 +0100 |
| commit | dc821c5f9ae5208ad1ec438718f75e224f856deb (patch) | |
| tree | 2c8c7c089e3196e1956fbb30a7088d6172a08104 /opcodes/i386-reg.tbl | |
| parent | eccab96d54a9455557d3c4d5bff431f6e526d0b7 (diff) | |
| download | fsf-binutils-gdb-dc821c5f9ae5208ad1ec438718f75e224f856deb.zip fsf-binutils-gdb-dc821c5f9ae5208ad1ec438718f75e224f856deb.tar.gz fsf-binutils-gdb-dc821c5f9ae5208ad1ec438718f75e224f856deb.tar.bz2 | |
x86: replace Reg8, Reg16, Reg32, and Reg64
Use a combination of a single new Reg bit and Byte, Word, Dword, or
Qword instead.
Besides shrinking the number of operand type bits this has the benefit
of making register handling more similar to accumulator handling (a
generic flag is being accompanied by a "size qualifier"). It requires,
however, to split a few insn templates, as it is no longer correct to
have combinations like Reg32|Reg64|Byte. This slight growth in size will
hopefully be outweighed by this change paving the road for folding a
presumably much larger number of templates later on.
Diffstat (limited to 'opcodes/i386-reg.tbl')
| -rw-r--r-- | opcodes/i386-reg.tbl | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 0c4e796..65b09be 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -21,7 +21,7 @@ // Make %st first as we test for it. st, FloatReg|FloatAcc, 0, 0, 11, 33 // 8 bit regs -al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval +al, Reg8|Acc, 0, 0, Dw2Inval, Dw2Inval cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval dl, Reg8, 0, 2, Dw2Inval, Dw2Inval bl, Reg8, 0, 3, Dw2Inval, Dw2Inval @@ -46,7 +46,7 @@ r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval // 16 bit regs -ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval +ax, Reg16|Acc, 0, 0, Dw2Inval, Dw2Inval cx, Reg16, 0, 1, Dw2Inval, Dw2Inval dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval @@ -63,7 +63,7 @@ r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval // 32 bit regs -eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval +eax, Reg32|BaseIndex|Acc, 0, 0, 0, Dw2Inval ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval @@ -79,7 +79,7 @@ r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval -rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0 +rax, Reg64|BaseIndex|Acc, 0, 0, Dw2Inval, 0 rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2 rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1 rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3 |