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| author | H.J. Lu <hjl.tools@gmail.com> | 2017-03-06 15:26:37 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2017-03-06 15:26:37 -0800 |
| commit | 603555e563725616246912711419637add54c961 (patch) | |
| tree | 9ccc0b32c73b8ff9017b49040ca4e6e9ea6456a8 /opcodes/i386-opc.h | |
| parent | 1cccfb31f5ba0dbc1cd3c679daf2f5b40252c6e0 (diff) | |
| download | fsf-binutils-gdb-603555e563725616246912711419637add54c961.zip fsf-binutils-gdb-603555e563725616246912711419637add54c961.tar.gz fsf-binutils-gdb-603555e563725616246912711419637add54c961.tar.bz2 | |
Add support for Intel CET instructions
Support Intel Control-flow Enforcement Technology (CET) instructions:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .cet.
* doc/c-i386.texi: Document cet.
* testsuite/gas/i386/cet-intel.d: New file.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/cet.s: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
* testsuite/gas/i386/i386.exp: Run Intel CET tests.
opcodes/
* i386-dis.c (REG_0F1E_MOD_3): New enum.
(MOD_0F1E_PREFIX_1): Likewise.
(MOD_0F38F5_PREFIX_2): Likewise.
(MOD_0F38F6_PREFIX_0): Likewise.
(RM_0F1E_MOD_3_REG_7): Likewise.
(PREFIX_MOD_0_0F01_REG_5): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
(PREFIX_0F1E): Likewise.
(PREFIX_MOD_0_0FAE_REG_5): Likewise.
(PREFIX_0F38F5): Likewise.
(dis386_twobyte): Use PREFIX_0F1E.
(reg_table): Add REG_0F1E_MOD_3.
(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
(three_byte_table): Use PREFIX_0F38F5.
(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
PREFIX_MOD_3_0F01_REG_5_RM_2.
* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
(cpu_flags): Add CpuCET.
* i386-opc.h (CpuCET): New enum.
(CpuUnused): Commented out.
(i386_cpu_flags): Add cpucet.
* i386-opc.tbl: Add Intel CET instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 140235f..9e4355c 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -208,6 +208,8 @@ enum CpuRDPID, /* PTWRITE instruction required */ CpuPTWRITE, + /* CET instruction support required */ + CpuCET, /* MMX register support required */ CpuRegMMX, /* XMM register support required */ @@ -233,7 +235,9 @@ enum /* If you get a compiler error for zero width of the unused field, comment it out. */ +#if 0 #define CpuUnused (CpuMax + 1) +#endif /* We can check if an instruction is available with array instead of bitfield. */ @@ -329,6 +333,7 @@ typedef union i386_cpu_flags unsigned int cpuospke:1; unsigned int cpurdpid:1; unsigned int cpuptwrite:1; + unsigned int cpucet:1; unsigned int cpuregmmx:1; unsigned int cpuregxmm:1; unsigned int cpuregymm:1; |