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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-07-30 16:13:02 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-07-30 16:13:17 -0700 |
| commit | 41eb8e88859b297f59f4d093aab9306d4b7057d9 (patch) | |
| tree | 0e7f36e6e8fd93e43e1f3d2df22a35eaa7e74a50 /opcodes/i386-opc.h | |
| parent | 5e500d33230ce2683001038177ad335365764793 (diff) | |
| download | fsf-binutils-gdb-41eb8e88859b297f59f4d093aab9306d4b7057d9.zip fsf-binutils-gdb-41eb8e88859b297f59f4d093aab9306d4b7057d9.tar.gz fsf-binutils-gdb-41eb8e88859b297f59f4d093aab9306d4b7057d9.tar.bz2 | |
x86: Add {disp16} pseudo prefix
Use Prefix_XXX for pseudo prefixes. Add {disp16} pseudo prefix and
replace {disp32} pseudo prefix with {disp16} in 16-bit mode test.
Check invalid {disp16}/{disp32} pseudo prefixes.
gas/
PR gas/26305
* config/tc-i386.c (_i386_insn::disp_encoding): Add
disp_encoding_16bit.
(parse_insn): Check Prefix_XXX for pseudo prefixes. Handle
{disp16}.
(build_modrm_byte): Handle {disp16}.
(i386_index_check): Check invalid {disp16} and {disp32} pseudo
prefixes.
* doc/c-i386.texi: Update {disp32} documentation and document
{disp16}.
* testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo.
* testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16}
tests.
* testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps
tests with 128-byte displacement. Add {disp16} tests.
* testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32}
vmovaps test. Add (%r13)/(%r13d) tests.
* testsuite/gas/i386/x86-64-inval-pseudo.l: New file.
* testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise.
* testsuite/gas/i386/inval-pseudo.l: Updated.
* testsuite/gas/i386/pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
opcodes/
PR gas/26305
* i386-opc.h (Prefix_Disp8): New.
(Prefix_Disp16): Likewise.
(Prefix_Disp32): Likewise.
(Prefix_Load): Likewise.
(Prefix_Store): Likewise.
(Prefix_VEX): Likewise.
(Prefix_VEX3): Likewise.
(Prefix_EVEX): Likewise.
(Prefix_REX): Likewise.
(Prefix_NoOptimize): Likewise.
* i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index b8a6dfc..09ee615 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -889,6 +889,18 @@ typedef struct insn_template #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */ #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ +/* Pseudo prefixes. */ +#define Prefix_Disp8 0 /* {disp8} */ +#define Prefix_Disp16 1 /* {disp16} */ +#define Prefix_Disp32 2 /* {disp32} */ +#define Prefix_Load 3 /* {load} */ +#define Prefix_Store 4 /* {store} */ +#define Prefix_VEX 5 /* {vex} */ +#define Prefix_VEX3 6 /* {vex3} */ +#define Prefix_EVEX 7 /* {evex} */ +#define Prefix_REX 8 /* {rex} */ +#define Prefix_NoOptimize 9 /* {nooptimize} */ + /* extension_opcode is the 3 bit extension for group <n> insns. This field is also used to store the 8-bit opcode suffix for the AMD 3DNow! instructions. |