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| author | H.J. Lu <hjl.tools@gmail.com> | 2007-04-18 16:13:15 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2007-04-18 16:13:15 +0000 |
| commit | 42903f7f5903fc4a27294aab1e23708c59a86b17 (patch) | |
| tree | 5e5e5c86c160605d02c3bd5d9663b0faf1776893 /opcodes/i386-opc.h | |
| parent | 026d3abbb22d4ac067a57d0a9aa2b2482266c9e7 (diff) | |
| download | fsf-binutils-gdb-42903f7f5903fc4a27294aab1e23708c59a86b17.zip fsf-binutils-gdb-42903f7f5903fc4a27294aab1e23708c59a86b17.tar.gz fsf-binutils-gdb-42903f7f5903fc4a27294aab1e23708c59a86b17.tar.bz2 | |
gas/
2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .sse4.1.
(process_operands): Adjust implicit operand for blendvpd,
blendvps and pblendvb in SSE4.1.
(output_insn): Support SSE4.1.
gas/testsuite/
2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add sse4.1 and x86-64-sse4.1.
* gas/i386/sse4_1.d: New file.
* gas/i386/sse4_1.s: Likewise.
* gas/i386/x86-64-sse4_1.d: Likewise.
* gas/i386/x86-64-sse4_1.s: Likewise.
opcodes/
2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (XMM_Fixup): New.
(Edqb): New.
(Edqd): New.
(XMM0): New.
(dqb_mode): New.
(dqd_mode): New.
(PREGRP39 ... PREGRP85): New.
(threebyte_0x38_uses_DATA_prefix): Updated for SSE4.
(threebyte_0x3a_uses_DATA_prefix): Likewise.
(prefix_user_table): Add PREGRP39 ... PREGRP85.
(three_byte_table): Likewise.
(putop): Handle 'K'.
(intel_operand_size): Handle dqb_mode, dqd_mode):
(OP_E): Likewise.
(OP_G): Likewise.
* i386-opc.c (i386_optab): Add SSE4.1 opcodes.
* i386-opc.h (CpuSSE4_1): New.
(CpuUnknownFlags): Add CpuSSE4_1.
(regKludge): Update comment.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 8e0a842..94ef037 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -69,6 +69,7 @@ typedef struct template #define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */ #define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */ #define CpuABM 0x200000 /* ABM New Instructions required */ +#define CpuSSE4_1 0x400000 /* SSE4.1 Instructions required */ /* These flags are set by gas depending on the flag_code. */ #define Cpu64 0x4000000 /* 64bit support required */ @@ -77,7 +78,8 @@ typedef struct template /* The default value for unknown CPUs - enable all features to avoid problems. */ #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \ - |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a) + |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \ + |CpuABM|CpuSSE4a) /* the bits in opcode_modifier are used to generate the final opcode from the base_opcode. These bits also are used to detect alternate forms of @@ -110,7 +112,9 @@ typedef struct template #define No_xSuf 0x800000 /* x suffix on instruction illegal */ #define FWait 0x1000000 /* instruction needs FWAIT */ #define IsString 0x2000000 /* quick test for string instructions */ -#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ +#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul + and special register processing for + some instructions. */ #define IsPrefix 0x8000000 /* opcode is a prefix */ #define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ #define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ |